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Fig. 1 | Nanoscale Research Letters

Fig. 1

From: CMOS-Compatible Top-Down Fabrication of Periodic SiO2 Nanostructures using a Single Mask

Fig. 1

Schematic of the process for fabricating periodic SiO2 nanostructures including nanoline, nanotrench, and nanohole arrays. a SiO2 nanostructures sample preparation, 1b-1e nanoline arrays fabrication process: 1b e-beam lithography; 1c α-Si mask is opened using the resist mask by RIE; 1d SiO2 nanoline arrays are produced by RIE; 1e α-Si mask is selectively removed using wet etch in TMAH solution. 2b-3e Nanotrench and nanohole arrays fabrication process using the same approach as 1b-1e

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