- Nano Express
- Open Access
Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around
© Guerfi and Larrieu. 2016
- Received: 29 January 2016
- Accepted: 4 April 2016
- Published: 19 April 2016
Nanowires are considered building blocks for the ultimate scaling of MOS transistors, capable of pushing devices until the most extreme boundaries of miniaturization thanks to their physical and geometrical properties. In particular, nanowires’ suitability for forming a gate-all-around (GAA) configuration confers to the device an optimum electrostatic control of the gate over the conduction channel and then a better immunity against the short channel effects (SCE). In this letter, a large-scale process of GAA vertical silicon nanowire (VNW) MOSFETs is presented. A top-down approach is adopted for the realization of VNWs with an optimum reproducibility followed by thin layer engineering at nanoscale. Good overall electrical performances were obtained, with excellent electrostatic behavior (a subthreshold slope (SS) of 95 mV/dec and a drain induced barrier lowering (DIBL) of 25 mV/V) for a 15-nm gate length. Finally, a first demonstration of dual integration of n-type and p-type VNW transistors for the realization of CMOS inverter is proposed.
- Plasma Etching
- Subthreshold Slope
- Short Channel Effect
- CMOS Inverter
- Drain Induce Barrier Lowering
The continuous demand of high-performance and low-power devices necessitates integration density enhancement, which pushes the CMOS technology to the ultimate nanoscale size dimension. Nanowire (NW) MOSFETs [1–5] are considered the most promising candidates to pursue the downscaling of MOS transistors, outperforming of triple gate FinFET architectures for sub-7-nm technology node. Indeed, nanowire architecture is more suitable for gate-all-around configuration to preserve the device immunity against the short channel effects (SCE) at such scaled dimensions [6, 7]. This architecture is speculated to bring CMOS scaling to the end of the transistor roadmap . The NW manufacturing method could be divided into two main approaches: bottom-up (BU) and top-down (TD). The first one suffers from process complexity  and metallic contamination issues since metallic nanoparticles are used as a catalyst. In contrast, the TD approach, using conventional microfabrication tools, is more suitable for nanoelectronic applications. It offers perfect control over dimensions, localization, and orientation which leads to highly efficient NW MOSFET devices [10–12]. The integration of the NW-based MOSFETs can be horizontal or vertical. From design analysis, vertical integration could give a better integration density of 50 % over the horizontal one [13, 14]. Moreover, gate-all-around definition in vertical configuration, even at nanoscale, is not defined by high-resolution lithography but simply by the thickness of deposited gate material [15, 16]. In this letter, we present a large-scale process for manufacturing of GAA vertical silicon nanowire (VNW) MOSFETs with a 15-nm gate length. The electrical performances will be discussed, in particular the influence of nanowire diameter on the device operation. Finally, a proof of concept for a CMOS inverter will be presented.
Before the implementation of platinum silicides (PtSi) for the realization of metallic source/drain contacts, the SiO2 layer is etched selectively by CCP mode plasma at both sides of the VNWs using a fluorine chemistry (CHF3:CF4:Ar = 20:20:10). The source contact is defined by a lift-off process. A 10-nm platinum layer is deposited by electron beam evaporation (anisotropic deposition), followed by the silicide reaction activation using a rapid thermal annealing (RTA) at 500 °C during 3 min under N2H2 (96 % 4 %) atmosphere. The VNW sidewalls are cleaned from platinum contaminations by a selective wet etching in aqua regia solution. Figure 2b presents a VNW network with silicided contacts at both sides of the VNWs with clean sidewalls. The 3D process completion must go through a perfect mastery of nanoscale layer engineering. To this end, an innovative planarization method to realize the source to gate isolation spacer was developed using the HSQ as a dielectric material . It is characterized by a low viscosity, providing excellent filling properties. Moreover, the HSQ is a CMOS-compatible material that offers a low dielectric constant (k ≈ 2.7), minimizing the parasitic capacitances. The planarization process was performed by chemical etching in highly diluted hydrofluoric acid (HF) in deionized water (1:1000). This approach has been preferred to plasma etching or chemical mechanical polishing (CMP); both approaches are widely used to planarize horizontal architectures but are not adapted to 3D architectures. However, the etching of the HSQ in diluted HF needs to take over bubble encroachments on the dielectric surface issued from the releasing of the hydrogen gas during SiOxHy etching that induces severe degradations leading to a rough surface. To prevent the bubble encroachment, a cationic surface agent, benzalkonium chloride, has been added to the diluted HF solution. This leads to the extraction of the gas bubbles as they appeared on the surface which then vanish in the solution. The resulting planarization is presented in Fig. 2c with a highly planarized HSQ layer over VNWs. It demonstrated an extremely flat layer, minimal roughness below 2 nm (measured by atomic force microscopy), without any degradation of the HSQ surface or of the VNWs. The etching rate of the HSQ is 2.3 nm/s, resulting in a highly controllable process. A 15-nm nickel layer is then deposited by electron beam evaporation over the gate to source spacer. The gate contact is performed by each back process after the definition of hard mask by photolithography step. The unprotected Ni layer is etched in chemical solution based on H2SO4:H2O2:EDI = 25:1:50 ml, followed by the photoresist stripping. For the proposed architecture, it is worth noting that the gate length is simply defined by the gate material thickness, without any high-resolution lithography step. A second spacer is then performed to insulate the gate to the drain contacts (Fig. 2d). Via openings are created by plasma etching in the dielectric to contact the metallic source and gate extensions. Finally, a 400-nm thick Al layer is deposited by sputtering followed by a chemical etch back in a solution of H3PO4:HNO3:EDI = 5:40:7. Finally, a forming gas anneal (FGA) (N2H2, 96 % 4 %) at 250 °C for 4 min is performed in order to passivate defects at both Si-SiO2 interface and at Si-PtSi contact interface .
A cross-section image of the device performed by transmission electron microscopy is presented in Fig. 2e and shows the 3D stacking composed of three conductive layers (source, gate, and drain contacts), separated by two insulating layers with homogenous thicknesses and without any defect or damage in the dielectric layers or wave effect at the vicinity of the NWs.
In summary, a large-scale process of Si VNW MOSFETs with nanoscale GAA is presented. The nanowire arrays were made by a top-down approach, and the vertical transistor was realized by a successive engineering of nanoscale thin films using conventional UV lithography. The electrical performances demonstrated excellent electrostatic behavior of the device for a 15-nm gate length, with very good immunity against short channel effects. Finally, a proof of concept for a CMOS inverter by dual integration of n- and p-type Si VNWs was proposed.
The authors wish to thank F. Cristiano and D. Troadec for TEM analysis. This work was supported by the French RENATECH network (French national nanofabrication platform).
Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
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