Fig. 1
From: Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-Around
Schematic 3D illustrations of the process steps of Si VNW GAA MOSFET. a Si VNW network patterning. b Gate oxide definition. c Metallic S/D contacts. d Gate to source isolating spacer. e Gate-all-around definition. f Drain to gate isolating spacer. g Metallic vias and contact pads