Fig. 2From: Vertical Silicon Nanowire Field Effect Transistors with Nanoscale Gate-All-AroundTilted SEM images of a Si VNW network of 25-nm diameter, b PtSi contacts at both side of VNW (c) and (d), respectively, gate to source and drain to gate insulating spacer formed by HSQ planarization technique and e TEM cross-section image of multilayer stacks implemented on VNW arraysBack to article page