- Nano Express
- Open Access
Electrical Characterization of Amorphous Silicon MIS-Based Structures for HIT Solar Cell Applications
© The Author(s). 2016
Received: 26 May 2016
Accepted: 5 July 2016
Published: 16 July 2016
A complete electrical characterization of hydrogenated amorphous silicon layers (a-Si:H) deposited on crystalline silicon (c-Si) substrates by electron cyclotron resonance chemical vapor deposition (ECR-CVD) was carried out. These structures are of interest for photovoltaic applications. Different growth temperatures between 30 and 200 °C were used. A rapid thermal annealing in forming gas atmosphere at 200 °C during 10 min was applied after the metallization process. The evolution of interfacial state density with the deposition temperature indicates a better interface passivation at higher growth temperatures. However, in these cases, an important contribution of slow states is detected as well. Thus, using intermediate growth temperatures (100–150 °C) might be the best choice.
Amorphous silicon layers are of particular interest for photovoltaic applications . In fact, as thin amorphous silicon (a-Si) layers saturate the crystalline silicon (c-Si) surfaces, the formation of recombination centers is avoided, and high quality interfaces are formed, which is of great interest for heterojunction with intrinsic thin layer (HIT) cells . This kind of solar cell consists of a crystalline/amorphous silicon heterojunction, and between both layers, a very thin film (~5 nm) of intrinsic amorphous silicon (i-a-Si:H) is introduced. The i-a-Si:H layer saturates the silicon surface dangling bonds, and therefore, this surface is passivated. Based on this technology, Panasonic achieved the efficiency world record with 25.6 % for silicon-based solar cells . Plasma-enhanced chemical vapor deposition (PECVD) is the most extended technique used to deposit a-Si:H [4, 5]. In this technique, the substrate and the plasma are very close, thus the substrate surface could be damaged by plasma bombardment. In this work, we used the electron cyclotron resonance chemical vapor deposition (ECR-CVD) technique to deposit the a-Si:H, which is a remote plasma procedure  that could reduce the damage to the c-Si surface. Other advantages of ECR-CVD are the possibility of in situ substrate plasma pre-treatment  and low processing pressure, which permits minimizing the contamination of the growing film . The possibility for scaling-up makes the ECR-CVD a very attractive technique for commercial solar cell fabrication.
As the aim of the intrinsic a-Si:H is the c-Si surface passivation, an interface study in depth is desirable. Previous works showed that the intrinsic amorphous silicon behaves as an insulator at low bias , and therefore, it is possible to apply the metal-insulator-semiconductor (MIS) characterization techniques in order to extract information from the a-Si:H/c-Si heterointerface. The density of interface defects can be related to the silicon surface dangling bonds, and its analysis is desirable in order to improve the a-Si:H quality .
In this work, we present a characterization of the interface between a-Si:H and c-Si. The results presented in this work support the use of a-Si:H thin films in HIT solar cells.
Metal—intrinsic amorphous silicon—semiconductor structures were fabricated as follows: 100 nm of intrinsic a-Si:H was deposited by ECR-CVD with an Astex-4500 reactor on n-type <100> silicon wafers with a resistivity of 1–10 Ωcm. Before deposition, the substrates were cleaned by a standard Radio Corporation America (RCA) cleaning  process, followed by a dip in diluted HF. The microwave power supply generator was 100 W. The precursor gas used was 19 sccm of 95 % Ar + 5 % SiH4. Four different deposition temperatures were used (30, 100, 150, and 200 °C). Metal electrodes (100 nm Ti + 200 nm Al) were deposited by e-beam evaporation. An annealing treatment was performed in forming gas atmosphere at 200 °C during 10 min by using RTP-600S equipment from Modular Process Technology Corp. The area of measured devices was 1.7 × 10−4 cm2. Fourier transform infrared spectroscopy (FTIR) measurements were performed by using a Nicolet Magna-IR 752 spectrometer, in a wave number range from 340 to 4000 cm−1.
As it was said before, due to its low carrier density, a-Si layers behave like insulator layers, so fabricated structures exhibit a similar behavior to MIS capacitors. Therefore, their study was carried out by using the electrical characterization techniques developed for MIS structures. Electrical measurements were carried out putting the sample in a light-tight, electrically shielded box. In order to record electrical parameters at temperatures from liquid nitrogen temperature (≈77 K), samples were cooled in an Oxford DM1710 cryostat. An Oxford ITC 502 temperature controller was used to keep the temperature constant while the electrical measurements are carried out. Current-voltage (I-V) curves were measured using the HP-4155B semiconductor parameter analyzer. Capacitance-voltage (C-V) and conductance-voltage (G-V) measurement setups involved a Keithley 4200SCS semiconductor analyzer. The experimental setup of the conductance transient technique consisted of an HP 3310A function generator to apply the bias pulses, an EG&G 5206 two-phase lock-in analyzer to measure the conductance, and an HP 54501A digital oscilloscope to record the complete conductance transients. Interface trap density (D it) was measured by deep-level transient spectroscopy (DLTS). These measurements were performed using a Boonton 72B capacitance meter, an HP 54501A digital oscilloscope to record the capacitance transients, and an HP 8112A pulse generator to bias the samples from inversion to accumulation. Finally, to obtain the flat-band voltage (V FB) transients, a feedback system varied the applied gate voltage accordingly to keep the capacitance at its flat-band value. An Agilent N6700B bias source, a Keithley 6517A electrometer, and a Boonton 72B capacitance meter were used for recording V FB transients.
Results and Discussion
The shape of C-V and G-V curves when voltage bias values increase can be attributed to the discharge process of slow states located far from the interface, which need high temperature or longer time to release their positive charge. When charge emission takes place, flat-band voltage moves towards more positive values, and so the hysteresis width of C-V curves diminishes. At the same time, the shoulder-shaped feature vanishes. As for G-V curves, the second peak moves to the right and its height diminishes. So, when the samples are driven from weak inversion to accumulation, the loss is due to the generation and recombination through both bulk and interfacial trap levels.
As indicated in Fig. 3a, these phenomena do not appear in samples grown at low temperatures, so the presence of slow traps in the a-Si layer bulk seems to be related to the growth processes carried out at temperatures above 150 °C.
Interfacial state density values for samples grown at temperatures of 100 °C and above are in the range of standard devices. Border trap densities and activation energy values are in the standard values as well. From our experimental results, the optimal amorphous/crystalline silicon interface is achieved for the highest growth temperature value. However, in samples grown at temperatures of above 150 °C, a significant presence of slow traps in the a-Si layer is detected. In conclusion, to use these kinds of structures in the HIT solar cell application field, growing a-Si layers at 100–150 °C seems to be the most adequate choice.
a-Si:H, hydrogenated amorphous silicon layers; c-Si, crystalline silicon; C-V, capacitance-voltage; D it, interface trap density; DLTS, deep-level transient spectroscopy; ECR-CVD, electron cyclotron resonance chemical vapor deposition; FTIR, Fourier transform infrared spectroscopy; G-V, conductance-voltage; HIT, heterojunction with intrinsic thin layer; i-a-Si:H, intrinsic amorphous silicon; I-V, current-voltage; MIS, metal-insulator-semiconductor; N DIGS, disorder-induced gap state density; PECVD, plasma-enhanced chemical vapor deposition; RCA, Radio Corporation America; V FB, flat-band voltage
The study has been supported by the Spanish TEC2014 under Grant Nos. 52152-C3-3-R and TEC2013-41730-R, funded by the Ministerio de Economía y Competitividad, and the P2013/MAE-2780 funded by the Comunidad de Madrid.
HC and IM conceived this study. RGH grew the samples with the help of JO and AP. HG, SD, and LB characterized the samples. HC wrote the manuscript with the input from all the authors. All authors read and approved the final version of the manuscript.
The authors declare that they have no competing interests.
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