Fig. 10From: Electrical Characterization of Amorphous Silicon MIS-Based Structures for HIT Solar Cell ApplicationsCapacitance and conductance vs. bias hysteresis loops measured at 500 kHz corresponding to a sample grown at 200 °C, at different temperatures, by using a voltage ramp (a), and at room temperature, by using a stair-shaped voltage, with different values of the step width (b–d). In all cases, the step of voltage bias was 20 mVBack to article page