Power- and Low-Resistance-State-Dependent, Bipolar Reset-Switching Transitions in SiN-Based Resistive Random-Access Memory
© The Author(s). 2016
Received: 25 June 2016
Accepted: 4 August 2016
Published: 12 August 2016
A study on the bipolar-resistive switching of an Ni/SiN/Si-based resistive random-access memory (RRAM) device shows that the influences of the reset power and the resistance value of the low-resistance state (LRS) on the reset-switching transitions are strong. For a low LRS with a large conducting path, the sharp reset switching, which requires a high reset power (>7 mW), was observed, whereas for a high LRS with small multiple-conducting paths, the step-by-step reset switching with a low reset power (<7 mW) was observed. The attainment of higher nonlinear current-voltage (I-V) characteristics in terms of the step-by-step reset switching is due to the steep current-increased region of the trap-controlled space charge-limited current (SCLC) model. A multilevel cell (MLC) operation, for which the reset stop voltage (V STOP) is used in the DC sweep mode and an incremental amplitude is used in the pulse mode for the step-by-step reset switching, is demonstrated here. The results of the present study suggest that well-controlled conducting paths in a SiN-based RRAM device, which are not too strong and not too weak, offer considerable potential for the realization of low-power and high-density crossbar-array applications.
Conventional memories such as dynamic random-access memory (DRAM) and NAND flash memory that are based on charge storage have been utilized in many applications until now, and the continually increasing demand for these memories is a response to the era of big data and the Internet of Things (IoT) [1, 2]. In recent years, however, and as expected, a near-future occurrence of the physical limits of these commercial memories has been identified. As an alternative, new approaches such as three-dimensional (3D) structure technology, multilevel cell (MLC) technology, and emerging memory technology have been widely researched [3–5]. Among the emerging memories, the resistive random-access memory (RRAM) has attracted considerable interest due to numerous advantages that include a simple structure, a fast switching speed, a low-voltage operation, an extendibility to the 3D structure, and an MLC operation [6–31]. Although extensive research has been carried out on the oxide-based RRAM that is a strong candidate for nonvolatile memory applications, it is also worth investigating a nitride-based RRAM with a silicon bottom electrode (BE), as it has a complete compatibility with the standard complementary metal-oxide-semiconductor (CMOS) processing [26–31]. So far, however, only a small amount of discussion regarding the resistive-switching characteristics of the nitride-based RRAM has occurred.
In particular, MLC is an important key technology for high-density nonvolatile memories and synaptic devices, as it overcomes the limits of conventional lithography . In the RRAM, the MLC can be easily achieved through a controlling of the stop voltage (V STOP) for reset switching. The main aim of this study is a clarification of the switching parameters to differentiate the three types of reset-switching transition in terms of a fabricated Ni/Si3N4/p + -Si-based RRAM device.
The sample was prepared as follows: After the standard cleaning processes, a p + Si BE was highly doped using a BF2 + ion implanting with a dose of 5 × 1015 cm−2 (converted to a peak concentration of 1020 cm−3). A SiN of 4.1 nm thickness was then deposited on the implanted silicon wafer using low-pressure chemical vapor deposition (LPCVD) at 785 °C after an annealing process was performed at 1050 °C for 10 min; subsequently, the Ni top electrode (TE) was deposited and patterned through a shadow mask that contains circular patterns with a 100-μm radii. All of the electrical properties were characterized at room temperature according to the DC voltage sweep mode and the pulse mode using the Keithley 4200-SCS semiconductor parameter analyzer (SPA) and the 4225-PMU ultra-fast I-V module, respectively. Also, the p + -Si BE was grounded and control biases were applied to the Ni TE over the measurements.
Results and Discussion
where θ is the free carrier density, θ t is the concentration of the traps, q is the electron charge, n 0 is the thermally produced free-electron density, L is the nitride thickness, ε r is the static-dielectric constant, and ε 0 is the permittivity of the free space. The trap-unfilled SCLC is changed to a trap-filled SCLC at the trap-filled limited voltage (V TFL), thereby resulting in a further slope increase. The sharp reset switching was finished before the V TFL was reached, while the switchings with the step-by-step reset and the weak reset were completed after the V TFL was reached.
The different bipolar reset transitions in terms of an Ni/SiN/Si RRAM device were investigated in this study depending on the reset power and the resistance value of the LRS, which is determined by the forming and set processes. The sharp reset switching was observed for the high reset power (>7 mW) and the low LRS, whereas the step-by-step reset switching was observed for the low reset power (<7 mW) and the high LRS. Higher nonlinear I-V characteristics and a gradual reset change regarding the step-by-step reset switching would be two of the most virtuous merits of the low-power and high-density crossbar array.
This work was supported by a grant from the National Research Foundation of Korea (NRF), funded by the Korea government (MSIP) (2015R1A2A1A01007307).
SK prepared the samples and electrical measurements and wrote the manuscript. BGP provided technical support to the study. Both authors read and approved the final manuscript.
The authors declare that they have no competing interests.
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