Design of High Performance Si/SiGe Heterojunction Tunneling FETs with a T-Shaped Gate
© The Author(s). 2017
Received: 28 September 2016
Accepted: 25 February 2017
Published: 16 March 2017
In this paper, a new Si/SiGe heterojunction tunneling field-effect transistor with a T-shaped gate (HTG-TFET) is proposed and investigated by Silvaco-Atlas simulation. The two source regions of the HTG-TFET are placed on both sides of the gate to increase the tunneling area. The T-shaped gate is designed to overlap with N+ pockets in both the lateral and vertical directions, which increases the electric field and tunneling rate at the top of tunneling junctions. Moreover, using SiGe in the pocket regions leads to the smaller tunneling distance. Therefore, the proposed HTG-TFET can obtain the higher on-state current. The simulation results show that on-state current of HTG-TFET is increased by one order of magnitude compared with that of the silicon-based counterparts. The average subthreshold swing (SS) of HTG-TFET is 44.64 mV/dec when V g is varied from 0.1 to 0.4 V, and the point SS is 36.59 mV/dec at V g = 0.2 V. Besides, this design cannot bring the sever Miller capacitance for the TFET circuit design. By using the T-shaped gate and SiGe pocket regions, the overall performance of the TFET is optimized.
Tunneling field-effect transistor (TFET) has become a kind of potential electric device for the ultralow power consumption applications [1–3]. Because band-to-band tunneling (BTBT) is the main operation mechanism in TFETs, TFETs can break the limitation of 60 mV/dec subthreshold swing (SS) in the conventional CMOS field-effect transistor that relies on the hot electron emission [4–6]. In addition, TFETs are less influenced by short channel effects than MOSFETs. However, the low on-state current is an inherent disadvantage in the traditional TFETs. In order to improve the on-state current of TFETs, various novel device structures have been proposed such as L-shaped channel TFET (LTFET) [7, 8], U-shaped channel TFET (UTFET) , L-shaped gate TFET (LG-TFET) , heterojunction TFET (HTFET) [11, 12]. Among these structures, the LG-TFET is proved to be essential for the enhancement of on-state current, because its tunneling current mainly depends on the electron BTBT perpendicular to the channel instead of parallel to the channel, and gate-pocket overlap regions in the lateral direction increase the electric field at the top of tunneling junction, which is helpful for the improvement of on-state current [10, 13, 14]. But electron BTBT in LG-TFET occurs only on one side of the gate, which will limit further improvement of on-state current.
In order to solve the above problem, a new heterojunction TFET with a T-shaped gate (HTG-TFET) is proposed. The proposed device structure remains vertical tunneling and places two source regions on both sides of the gate to further increase tunneling area. The T-shaped gate overlaps with the pocket regions in the lateral direction to increase the electric field at the top of tunneling junction. In addition, the heterojunctions between SiGe pocket regions and silicon source regions promote energy band to bend sharply . TCAD simulation results show that proposed HTG-TFET gains higher on-state current and lower SS than both LG-TFET and UTFET.
The proposed HTG-TFET structure is investigated with Silvaco ATLAS simulation tool using the non-local BTBT model. The non-local BTBT model takes into account the spatial variation of the energy band, and it also considers that the generation/recombination of the opposite carrier type is not spatially coincident. So, the non-local BTBT can model the tunneling process more accurately . A lot of work has demonstrated that TFETs simulated by non-local BTBT are in accord with the experiments [8, 10, 18]. Since the source regions are highly doped, the band gap narrowing model and Fermi-Dirac statistics are included. The Shockley-Read-Hall recombination and Lombardi mobility models are also adopted in the simulations. Moreover, the gate leakage current is ignored.
The simulation parameters of the proposed device are as follows: thickness of the N+ pocket is 5 nm (T p); height of the source regions and drain region is 40 nm (H s) and 20 nm (H d), respectively; length and height of the gate are 10 nm (L g) and 60 nm (H g), respectively; thickness of the gate oxide (HfO2) is 2 nm (T ox); length of gate-pocket overlap is 7 nm (L ov). What is more, gate work function φ is 4.33 eV; doping concentrations of P+ source regions (N s) and N+ drain region (N d) are 1 × 1020/cm3 and 1 × 1018/cm3, respectively; doping concentration of N+ pockets (Np) is 1 × 1019/cm3.
Results and Discussion
Finally, the capacitance characteristics of HTG-TFET, LG-TFET, and UTFET are also investigated by using an AC small signal simulation with the operating frequency of 1 MHz. In the TFETs, due to the presence of source-side tunneling barrier, the gate-to-source capacitance (C gs ) is very small. Therefore, the Miller capacitance mainly depends on the gate-to-drain capacitance (C gd ) [19, 20].
In this paper, a novel heterojunction TFET with a T-shaped gate (HTG-TFET) is proposed and its advantages over other counterparts are studied using Silvaco-Atlas simulation. Due to the overlap of gate and pocket in both the vertical and the lateral directions, the tunneling area and electric field at the top of tunneling junction are enhanced so that on-state drain current increase obviously. Moreover, the heterojunctions formed between silicon source and SiGe pocket regions help device to obtain better performance. Although dual sources in HTG-TFET increase C gs , the reduced C gd cannot bring sever Miller capacitance. The parameters that affect the performance of HTG-TFET, including L ov, N p, T p, and N s, are also investigated by simulations. On the premise that optimal parameters are used in simulations, the HTG-TFET obtains the optimum performance that on-state current is 7.02A/μm, average SS is 44.64 mV/dec, and point SS is 36.59 mV/dec at V g = 0.2 V. Therefore, HTG-TFET can be a potential candidate for the next generation of low-power electron device.
We acknowledge the Project of National Natural Science Foundation of China and the valuable suggestions from the peer reviewers.
The role of the Project of National Natural Science Foundation of China (61504100) is designing the work; the role the Project of National Natural Science Foundation of China (61434007) is the collection, analysis, and interpretation of the data.
WL generated the research idea, analyzed the data, and wrote the paper. WL and SpC carried out the simulation. WL, SpC, and ZnY participated in the discussion. SlW and HxL have given the final approval of the version to be published. All authors read and approved the final manuscript.
WL and SpC are Ph.D students in Xidian University. SlW is a doctor in Xidian University. HxL is a professor in Xidian University. ZnY is a doctor in Xi’an University of Technology.
The authors declare that they have no competing interests.
Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
- Wang PF, Hilsenbeck K, Nirschl T, Oswald M, Stepper C, Weis M et al (2004) Complementary tunneling transistor for low power application. Solid State Electron 48(12):2281–2286View ArticleGoogle Scholar
- Seabaugh AC, Zhang Q (2010) Low-voltage tunnel transistors for beyond CMOS logic. Proc IEEE 98(12):2095–2110View ArticleGoogle Scholar
- Villalon A, Carval GL, Martinie S, Royer CL, Jaud MA, Cristoloveanu S (2014) Further insights in TFET operation. IEEE Trans Electron Devices 61(8):2893–2898View ArticleGoogle Scholar
- Choi WY, Park BG, Lee JD, Liu TJK (2007) Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) Less than 60 mV/dec. IEEE Electron Device Lett 28(8):743–745View ArticleGoogle Scholar
- Ganapathi K, Alahuddin S (2011) Heterojunction vertical band-to-band tunneling transistors for steep subthreshold swing and high on current. IEEE Electron Device Lett 32(5):689–691View ArticleGoogle Scholar
- Wang P, Tsui B (2016) Band engineering to improve average subthreshold swing by uppressing low electric field band-to-band tunneling with epitaxial tunnel layer funnel FET structure. IEEE Trans Nanotechnol 15(1):74–79View ArticleGoogle Scholar
- Kim SW, Choi WY, Sun MC, Kim HW, Park BG (2012) Design guideline of Si-based L-shaped tunneling field-effect transistors. Jpn J Appl Phys 51(6S):06FE09-1–06FE09-4Google Scholar
- Kim SW, Kim JH, Liu TJK, Choi WY, Park BG (2016) Demonstration of L-shaped tunnel field-effect transistors. IEEE Trans Electron Devices 63(4):1774–1778View ArticleGoogle Scholar
- Wang W, Wang PF, Zhang CM, Lin X, Liu XY, Sun QQ et al (2014) Design of U-shape channel tunnel FETs with SiGe source regions. IEEE Trans Electron Devices 61(1):193–197View ArticleGoogle Scholar
- Yang ZN (2016) Tunnel field-effect transistor with an L-shaped gate. IEEE Electron Device Lett 37(7):839–842View ArticleGoogle Scholar
- Singh G, Amin SI, Anand S, Sarin RK (2016) Design of Si0.5Ge0.5 based tunnel field effect transistor and its performance evaluation. Superlattice Microstruct 92:143–156View ArticleGoogle Scholar
- Asthana PK, Ghosh B, Goswami Y, Tripathi BMM (2014) High-speed and low-power ultradeep-submicrometer III–V heterojunctionless tunnel field-effect transistor. IEEE Trans Electron Devices 61(2):479–486View ArticleGoogle Scholar
- Kao KH, Verhulst AS, Vandenberghe WG, Sorée B, Magnus W, Leonelli D et al (2012) Optimization of gate-on-source-only tunnel fets with counter-doped pockets. IEEE Trans Electron Devices 69(8):2070–2077View ArticleGoogle Scholar
- Mallik A, Chattopadhyay A, Guin S, Karmakar A (2013) Impact of a spacer–drain overlap on the characteristics of a silicon tunnel field-effect transistor based on vertical tunneling. IEEE Trans Electron Devices 60(3):935–943View ArticleGoogle Scholar
- Kim HW, Kim JH, Kim SW, Sun MC, Park E, Park BG (2014) Tunneling field-effect transistor with Si/SiGe material for high current drivability. J Appl Phys 53(6S):06JE12-1–06JE12-4Google Scholar
- Vandooren A, Leonelli D, Rooyackers R, Hikavyy A, Devriendt K, Demand M et al (2013) Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction tunnel-FETs. Solid State Electron 83:50–55View ArticleGoogle Scholar
- SILVACO International, Santa Clara, CA 95054, USA, ATHENA/ATLAS User’s Manual (2012)Google Scholar
- Choi WY, Lee HK (2016) Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs). Nano Convergence 3(13):1–15Google Scholar
- Saurabh M, Ramakrishnan K, Suman D, Vijaykrishnan N (2009) Effective capacitance and drive current for tunnel fet (TFET) CV/I estimation. IEEE Trans Electron Devices 56(9):2092–2098View ArticleGoogle Scholar
- Saurabh M, Ramakrishnan K, Suman D, Vijaykrishnan N (2009) On enhanced Miller capacitance effect in interband tunnel transistors. IEEE Electron Device Lett 30(10):1102–1104View ArticleGoogle Scholar