- Nano Express
- Open Access

# Time-Shared Twin Memristor Crossbar Reducing the Number of Arrays by Half for Pattern Recognition

- Son Ngoc Truong
^{1}, - Khoa Van Pham
^{1}, - Wonsun Yang
^{1}, - Anjae Jo
^{2}, - Mi Jung Lee
^{2}, - Hyun-Sun Mo
^{1}Email author and - Kyeong-Sik Min
^{1}Email authorView ORCID ID profile

**Received:**3 December 2016**Accepted:**1 March 2017**Published:**21 March 2017

## Abstract

In this paper, we propose a new time-shared twin memristor crossbar for pattern-recognition applications. By sharing two memristor arrays at different time, the number of memristor arrays can be reduced by half, saving the crossbar area by half, too. To implement the time-shared twin memristor crossbar, we also propose CMOS time-shared subtractor circuit, in this paper. The operation of the time-shared twin memristor crossbar is verified using 3 × 3 memristor array which is made of aluminum film and carbon fiber. Here, the crossbar array is programmed to store three different patterns. When we apply three different input vectors to the array, we can verify that the input vectors are well recognized by the proposed crossbar. Moreover, the proposed crossbar is tested for the recognition of complicated gray-scale images. Here, 10 images with 32 × 32 pixels are applied to the proposed crossbar. The simulation result verifies that the input images are recognized well by the proposed crossbar, even though the noise level of each image is varied from −10 to +10 dB.

## Keywords

- Time-shared twin memristor crossbar
- Twin memristor crossbar
- Pattern recognition

## Background

Memristor crossbars have been studied for many years for neuromorphic pattern recognitions [1–5]. Memristor crossbars can be thought very suitable to pattern recognition, in which all the columns of crossbar can be compared with the input pattern to find the best match simultaneously. Once the best-matched column is decided, the rest of columns are inhibited according to winner-take-all algorithm [3, 4].

Memristors which are used in pattern recognition can be either analog or binary. If we use analog memristor which can change its memristance gradually, pattern matching can be more accurate and demand a smaller number of memristors in crossbar array [6, 7]. However, analog memristor is more difficult to fabricate and more susceptible to noise and statistical variation than binary memristor [3]. Moreover, the number of memristive materials that show analog behavior is much smaller than the number of binary memristors. Based on these facts, binary memristors are used in pattern-matching crossbar, in this paper.

For the pattern-matching crossbar, we already proposed twin memristor crossbar (TMC) which could replace complementary memristor crossbar (CMC) [4]. CMC uses two memristor arrays of M^{+} and M^{−} to perform the exclusive NOR (XNOR) operation, where the M^{+} and M^{−} arrays are applied by the input vector and the inversion, respectively [3]. One thing to note here is that the number of low-resistance state (LRS) is very important in terms of sneak-path leakage because the leakage current flows mainly through LRS rather than high resistance state (HRS). In CMC, the total number of LRS in M^{+} and M^{−} arrays cannot be reduced at all, even though we use image compression algorithms such as discrete cosine transform (DCT) [4]. In CMC, M^{+} and M^{−} arrays are complementary to each other [3, 4]. It means that the same number of LRS in M^{−} array is increased always, though we reduce the number of LRS in M^{+} array using DCT [4]. Thus, the image compression becomes meaningless in CMC.

Unlike CMC, TMC uses two identical M^{+} arrays for performing XNOR operation. It means that the total number of LRS in the two identical arrays can be significantly reduced by using DCT, as explained well in the previous publication [4]. Based on TMC, we propose to apply a new time-sharing concept to TMC for reducing the number of TMC arrays by half, in this paper.

## Method

^{+}arrays. Here, the time-sharing concept is not used in Fig. 1a. The XNOR operation in TMC is expressed by the following Eq. (1) [4].

Using Eq. (1), we can measure the amount of similarity between the input vector and the stored pattern in TMC arrays. Here, the input vector is represented by *a*
_{0}, *a*
_{1}, …, *a*
_{
n − 1} which enters the upper M^{+} array. *a*
^{'}
_{0}, *a*
^{'}
_{1}, …, *a*
^{'}
_{
n − 1} are the inversion of the input vector *a*
_{0}, *a*
_{1}, …, *a*
_{
n − 1} which enters the lower M^{+} array in Fig. 1a. The pattern stored at column j is represented by *g*
_{0,j
}, *g*
_{1,j
}, …, *g*
_{
n − 1,j
}. I_{0} is the inverter in Fig. 1a. S_{0} and W_{0} are the subtractor and weighting circuit, respectively, in Fig. 1a. S_{0} and W_{0} can be designed using CMOS current mirror very easily [4]. \( {y}_j^{+} \) and \( {y}_j^{-} \) can be obtained from the jth column currents of the upper M^{+} and lower M^{+} arrays, respectively, in Fig. 1a. *y*
_{
j
} means the amount of similarity of jth column with the input vector. Here, we assume that two jth columns in the upper and lower M^{+} arrays can store the same image in Fig. 1a. The number of columns in M^{+} array is as many as “m,” as shown in Fig. 1a. If we compare *y*
_{
j
} values from j = 0 to m−1, we can know the largest *y*
_{
j
} means the best matched column with the input vector. The largest *y*
_{
j
} can be chosen by the winner-take-all circuit, as shown in Fig. 1a [3, 4].

^{+}arrays. These two identical arrays are applied by the input vector,

*a*

_{0},

*a*

_{1}, …,

*a*

_{ n − 1}, and the inversion,

*a*

^{'}

_{0},

*a*

^{'}

_{1}, …,

*a*

^{'}

_{ n − 1}, respectively, as shown in Fig. 1a. These two arrays can be time-shared by applying

*a*

^{'}

_{0},

*a*

^{'}

_{1}, …,

*a*

^{'}

_{ n − 1}and

*a*

_{0},

*a*

_{1}, …,

*a*

_{ n − 1}, respectively, at different time, as shown in Fig. 1b. This is possible because both the input vector and its inversion are applied to the same array of M

^{+}in Fig. 1b. By doing so, the time-sharing array can reduce the number of memristors by half, resulting in a great amount of area reduction. The operation of the time-shared TMC with two phases can be explained as follows. Here, for the first phase at t = k−1, we apply the inversion of input,

*a*

^{'}

_{0},

*a*

^{'}

_{1}, …,

*a*

^{'}

_{ n − 1}, to M

^{+}array. At the following second phase at t = k, we apply the input vector,

*a*

_{0},

*a*

_{1}, …,

*a*

_{ n − 1}, to the same M

^{+}array with the previous time. By doing so, the input vector,

*a*

_{0},

*a*

_{1}, …,

*a*

_{ n − 1}, and the inversion,

*a*

^{'}

_{0},

*a*

^{'}

_{1}, …,

*a*

^{'}

_{ n − 1}, can share the same M

^{+}array at different time, respectively. The advantage of time-shared M

^{+}array is array-area reduction. In Fig. 1b, the array area can be reduced by half, compared to two M

^{+}arrays in Fig. 1a. I

_{0}is the simple inverter, in Fig. 1b. Here, the multiplexer X

_{0}and de-multiplexer D

_{0}are controlled by the timing signal, CLK. When CLK is low, the inverted input enters the crossbar and we can obtain \( {y}_j^{-}={\displaystyle \sum_{i=0}^{n-1}{a}_i^{\hbox{'}}{g}_{i, j}} \) from the de-multiplexer D

_{0}. When CLK is high, the input vector is applied to M

^{+}and the de-multiplexer D

_{0}delivers \( {y}_j^{+}={\displaystyle \sum_{i=0}^{n-1}{a}_i{g}_{i, j}} \) to the time-shared subtractor S

_{0}which will be shown in Fig. 2b. W

_{0}is the weighting circuit in Fig. 1b. One more thing to note here is timing overhead due to the two-phase operation in Fig. 1b. The overall operation time in pattern recognition includes not only the time of crossbar array but also the time of winner-take-all circuit. Usually, because the time needed in the winner-take-all circuit is much longer than the time of crossbar operation, the overhead of two-phase operation of Fig. 1b can be ignored. Compared to negligible overhead of the two-phase operation in Fig. 1b, the array-area reduction is obviously as large as 50%.

Figure 2a shows the detailed schematic of the proposed time-shared TMC in Fig. 1b for recognizing 10 images from the image #0 to the image #9. M_{0,0}, M_{0,1}, M_{0,2}, and M_{0,3} are memristors which correspond to the 0th pixel of the image #0. The image #0 is stored from the 0th row to 1023rd row. M_{1023,0}, M_{1023,1}, M_{1023,2}, and M_{1023,3} are for the 1023rd pixel of the image #0. M_{1023,0}, M_{1023,1}, M_{1023,2}, and M_{1023,3} should be weighted by ×1, ×2, ×4, and ×8, respectively, using the simple current mirror circuit, as explained in [4]. M_{0,0} is applied by a_{0}<0> and the inversion a’_{0}<0>, respectively, at different time, which is controlled by CLK signal. Similarly, M_{0,3} is applied by a_{0}<3> and a’_{0}<3>, at different time. COL_{0,0}, COL_{0,1}, COL_{0,2}, and COL_{0,3} are for calculating the pattern-matching current of the image #0, with the weight of 1, 2, 4, and 8, respectively. In Fig. 2a, I_{0} and I_{1023} are the simple inverters, for a_{0} and a_{1023}, respectively. X_{0} and X_{1023} are the multiplexers for a_{0} and a_{1023}, respectively. D_{3} is the de-multiplexer for COL_{0,3}. S_{3} and W_{3} are the subtractor and weighting circuit for COL_{0,3}, respectively. The column current of COL_{0,3} is delivered to IC_{3} which is composed of D_{3}, S_{3}, and W_{3} in Fig. 2a, for COL_{0,3}. The detailed schematic of IC_{3} is shown in Fig. 2b. The winner-take-all circuit can decide the best match array with the input image among 10 arrays which store 10 images, respectively.

Figure 2b shows the time-shared subtractor, IC_{3}, for the column COL_{0,3} in Fig. 2a. IC_{3} is composed of D_{3}, S_{3}, and W_{3}, as shown in Fig. 2a. The IC_{3} circuit has two phases of operation, which are the phase I and the phase II, respectively. Simply explaining, I^{−} current is measured during the phase I and I^{+}–I^{−} current is calculated using the previously measured I^{−} during the phase II. If we look at Fig. 2b, the amount of \( {I}_{0,3}^{-} \) is obtained from the COL_{0,3} and stored in C_{1}, during the phase I, for the inverted input of *a*
^{'}
_{0}, *a*
^{'}
_{1}, …, *a*
^{'}
_{
n − 1}. At this time, S_{1} and S_{2} are on and S_{3} is off. During the following phase II, S_{1} and S_{2} are off and S_{3} is on. During this phase II, \( {I}_{0,3}^{+} \) is measured from the COL_{0,3} and \( {I}_{0,3}\left(={I}_{0,3}^{+}-{I}_{0,3}^{-}\right) \) is calculated by the current mirror circuit of M_{1}, M_{2}, and M_{3}. Here, the subtraction is performed by the current of M_{2} which can recall \( {I}_{0,3}^{-} \), stored at C_{1} during the previous phase I, as shown in Fig. 2b. Here, it can be noted that the de-multiplexer function can be realized by controlling three switches of S_{1}, S_{2}, and S_{3}. The subtraction can be performed by the current mirror circuit of M_{1}, M_{2}, and M_{3}. The weighting is realized by sizing of M_{3} and M_{4}, in Fig. 2b. Similarly, \( {I}_{0,2}\left(={I}_{0,2}^{+}-{I}_{0,2}^{-}\right) \), \( {I}_{0,1}\left(={I}_{0,1}^{+}-{I}_{0,1}^{-}\right) \), and \( {I}_{0,0}\left(={I}_{0,0}^{+}-{I}_{0,0}^{-}\right) \) are also calculated from IC_{2}, IC_{1}, and IC_{0}, respectively, in Fig. 2a. *I*
_{0,3}, *I*
_{0,2}, *I*
_{0,1}, and *I*
_{0,0} are added to each other and the weighted sum *I*
_{0}(=8*I*
_{0,3} + 4*I*
_{0,2} + 2*I*
_{0,1} + *I*
_{0,0}) is delivered to the winner-take-all circuit, in Fig. 2a [3, 4]. In the winner-take-all, *I*
_{0} of the image #0 is compared with the other currents of *I*
_{1}, …, *I*
_{9} from the image #1 to the image #9.

The detailed timing diagram of the time-shared subtractor is shown in Fig. 2c. During the phase I, when S_{1} and S_{2} are on and S_{3} is off, the circuit IC_{3} in Fig. 2b measures \( {I}_{0,3}^{-} \) and stores the measured amount of \( {I}_{0,3}^{-} \) for the inverted input vector, at the capacitor C_{1}. From Fig. 2c, V_{C1} represents the amount of current of \( {I}_{0,3}^{-} \) which is converted to the capacitor’s voltage, during the phase I. During the following phase II, S_{1} and S_{2} become off and S_{3} is on. We can calculate an amount of \( {I_{0,3}}^{+}-{I}_{0,3}^{-} \) by measuring *I*
_{0,3}
^{+} and recalling \( {I}_{0,3}^{-} \) which was stored at C_{1} from the previous phase I. In Fig. 2b, we used the weighting factor as large as 8, resulting in \( 8\times \left({I_{0,3}}^{+}-{I}_{0,3}^{-}\right) \) in Fig. 2c.

## Results and Discussion

For testing the pattern recognition of the time-shared TMC, we applied three different input vectors to the crossbar, which are [LHH], [HHL], and [HLH], respectively. Figure 4b shows the measured currents of three columns when we apply the input vector [LHH] and its inversion [HLL] to the time-shared crossbar, respectively. The measurement shows that the first column’s current is the largest among the three columns. Thus, the following winner-take-all circuit can choose the first column as a winner. When we apply the input vector [HHL] and the inversion [LLH], respectively, at different time, the time-shared subtractor measured the *I*
^{+} − *I*
^{−} values for three columns. Comparing the three currents, the measurement shows the second column has the largest current, as shown in Fig. 4c. Similarly, the third column was measured to have the largest current among three columns, for the input vector [HLH] and its inversion [LHL], as indicated in Fig. 4d.

## Conclusions

In this paper, we proposed the time-shared TMC for pattern-recognition applications. By sharing two memristor arrays at different time, the number of memristor arrays can be reduced by half, saving the crossbar’s area by about half. To implement the time-shared TMC, we designed and verified the CMOS time-shared subtractor by the circuit simulation. The operation of the time-shared TMC was experimentally verified using the fabricated 3 × 3 memristor array which was made of aluminum film and carbon fiber. Here, we programmed the array to store three different patterns. By applying three different input vectors to the time-shared TMC, we could verify that the input vectors were recognized well by the proposed circuits. Moreover, the proposed time-shared TMC was tested for the recognition of more complicated gray-scale images. Here, 10 gray-scale images with 32 × 32 pixels were tested and verified to be recognized well by the proposed time-shared TMC, even though the noise level was varied from −10 to +10 dB.

## Declarations

### Acknowledgements

The work was financially supported by NRF-2011-0030228, NRF-2015R1A5A7037615, NRF-2016R1A6A3A01006588, and KIST Open Research Program (ORP). The CAD tools were supported by IC Design Education Center (IDEC), Daejeon, Korea.

### Authors’ Contributions

All authors have contributed to the submitted manuscript of the present work. HSM and KSM defined the research topic. SNT designed the circuit and performed the simulation. KSM wrote the paper. All authors read and approved the submitted manuscript.

### Authors’ Information

SNT, KVP, and WSY are the post-doc researcher, the Ph.D, and the M.S. students, respectively, who are studying at the School of Electrical Engineering, Kookmin University, Seoul, Korea. HSM and KSM are the professors at the School of Electrical Engineering, Kookmin University, Seoul, Korea. AJ and MJL are the M.S. student and the professor, respectively, at the School of Advanced Material Engineering, Kookmin University, Seoul, Korea.

### Competing Interests

The authors declare that they have no competing interests.

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## Authors’ Affiliations

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