Fig. 4
From: Multi-Layer SnSe Nanoflake Field-Effect Transistors with Low-Resistance Au Ohmic Contacts
a Drain current (I d) as a function of applied source-drain voltage (V ds), for the gate voltages (V g) of −30, 0, and 30 V, for a 90-nm-thick SnSe nanoflake FET, at room temperature. b I d vs. V ds for V g ranging from −40–40 V in steps of 10 V, for the 90-nm-thick SnSe nanoflake FET. The inset shows I d vs. V g for V ds of 0.8 and 1.0 V, measured at room temperature. c I d vs. V ds without biasing V g (=0) for Au and Ti contacts on a SnSe nanoflake FET. The inset shows an AFM scanned image of SnSe nanoflakes. d Schematics of the energy band diagrams of two metals, Au and Ti, on p-type SnSe semiconductors