- Nano Express
- Open Access
A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
© The Author(s). 2017
- Received: 14 April 2017
- Accepted: 9 June 2017
- Published: 15 June 2017
This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application. With compact cell area and full logic compatibility, this new nv-SRAM incorporates two STI-ReRAMs embedded inside the 4T SRAM. Data can be read/write through a cross-couple volatile structure for maintaining fast accessing speed. Data can be non-volatilely stored in new SRAM cell through a unique self-inhibit operation onto the resistive random access memory (RRAM) load, achieving zero static power during data hold.
- CMOS logic process
- Static random access memory
- Resistive random access memory
- Logic non-volatile memory
In recent years, various low-power static random access memories have been developed for meeting the need in computing systems on portable devices and IOT applications [1–6]. As CMOS technology scales down to nano-meter regime, the off-state leakage current increases drastically, which leads to worsen static power consumption for volatile memory modules [7, 8]. The static power consumption raised by the leakage current in nano-scaled transistors has become one of the key challenges for the advancement of low-power SRAMs. [9–11]. Over the years, different cell structures or operation techniques [12–16] have been proposed for minimizing power consumption in SRAMs. Some of the newly proposed cells incorporate non-volatile storage elements, such as resistive random access memory (RRAM) and magnetoresistive random access memory (MRAM) [17–20], to achieve zero-holding power while maintaining low operation power and fast accessing speed in processing volatile data. However, adding non-volatile storage elements onto logic-based SRAM arrays generally requires additional layers and/or processes to the standard logic platforms [21–23]. This will unavoidably increase process complexity to their development. In addition, these back-end-based RRAMs and MRAMs require large connecting structure, composed of multi-stack of vias and metals to the SRAM cells. These bridging structures increase parasitic capacitance to the SRAM data storage node, affecting the accessing speed of these non-volatile SRAM cells [24, 25]. In our previous work , a new zero static power 4T nv-SRAM with STI-sidewall RRAMs located next to the floating storage nodes of 4T SRAM has been firstly proposed. In this letter, this 4T2R nv-SRAM featuring non-volatile data storage, zero-holding power and fast accessing speed will further analyzed and optimized for embedded NVM applications.
STI-ReRAM Cell Structure
Non-volatile SRAM Concept
In its initial states, STI-RRAM typically carries a resistance level of 108 Ω, while the TMO film is intact. Through a blanket forming operation, the nv-SRAM cells can be initialized simultaneously in a block by block fashion at VD = 2.8 V. Both RL1 and RL2 (loading resistance on the left and right, respectively) are initialized to RL,L. The final RL,L level of 20~370 kΩ can be controlled by giving different WL voltage during forming operation. The cell then reaches a balance state, meaning that the two loading resistors are at the same state. In this state, this cell can now function as the typical 4T2R SRAM, processing volatile data in a conventional way, by storing data in the cross-coupled latch.
To store the data non-volatilely, the complimentary latched data can be stored onto the RRAMs by a self-inhibit mechanism inherit in this cell. When the data is successfully stored in the RRAM pair, one can turn off the supply power for permanent data hold. To access the stored state, simply re-apply VDD to the array. The non-volatile data will be restored to the Q and QB nodes automatically and can be accessed through conventional SRAM read mode. Finally, to refresh the non-volatile data, a blanket set operation is applied to the SRAM arrays so that the array will return to its balance states.
Nv-SRAM cell operation conditions
1.1 V (VDD)
2 V (VPP)
NV data read
1.1 V (VDD)
Parasitic Effect and Comparison
By incorporating the full logic compatible STI-RRAM into this new SRAM cell, this cell can be easily implemented by most standard logic process without adding masking layers as well as process steps. This feature can great enhance its applications and flexibility in various non-volatile memory IP modules needed in many IC systems. In addition, the proposed 4T2R nv-SRAM features much smaller parasitic capacitance comparing to other previously reported nv-SRAMs [29–31] which require back-end-of-line (BEOL) non-volatile components. In order to connect the Q and QB node from the surface of Si to these BEOL RRAM or MRAMs, multiple stacks of metal and via layers are needed. These large bridging structures lead to significant parasitic RC effect. Large parasitic capacitance introduced to the internal nodes inside the SRAM cells can critically affect the response time of the devices.
Much smaller parasitic capacitance of this embedded nv-SRAM can lead to faster response time during dynamic read operation in the SRAM cell. This prevents the large internal capacitance of the connecting bridge impact on response time of the logic-based SRAM array.
Variation-Induced Static Noise Margin Degradation
A novel 4T2R STI-RRAM-based non-volatile SRAM fully logic compatible to CMOS logic process has been successfully demonstrated in pure CMOS logic process at 40 nm technology node without extra masks or steps. This nv-SRAM cell features self-inhibit, self-restore mechanism for non-volatile data, small parasitic capacitance on latch nodes, and zero static power during data hold. These superior characteristics make STI-RRAM-based nv-SRAM a promising solution for low-power/high-speed logic non-volatile memory applications in the future.
The author would like to thank the support from the Ministry of Science and Technology (MOST), Taiwan, and Taiwan Semiconductor Manufacturing Company (TSMC).
MY and CF carried out the device measurement, analysis, and writing of the manuscript. YH carried out the references research. CJ and YC conceived of this study and carried out the manuscript modification. All authors read and approved the final manuscript.
The authors declare they have no competing interests.
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