Fig. 12From: A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic ProcessParasitic capacitance on the latch nodes of nv-SRAM cells from ref [30] and that from this work based on 40 nm CMOS technology, significant increase in parasitic capacitance is found as the number of metal layer increasesBack to article page