Fig. 5From: A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process a 3D illustration of the proposed 4T2R nv-SRAM cell structure and the b corresponding cross-sectional TEM picture. c The circuit schematic of a SRAM cell is shown with two RRAM resistors as the loading devicesBack to article page