Fig. 8
From: A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
a The read static noise margin (SNM) of the proposed SRAM cells with different WL voltage during initialization. Reasonable SNM can be maintained within a fairly large range of RL,L of 20~400 kΩ. b Dynamic read and write characteristics of a cell under balance load condition reveal good response time within nano-seconds. Higher RL,L slightly reduces the pull-up speed during write operation