Amorphous Silicon Nanowires Grown on Silicon Oxide Film by Annealing
© The Author(s). 2017
Received: 5 April 2017
Accepted: 26 July 2017
Published: 10 August 2017
In this paper, amorphous silicon nanowires (α-SiNWs) were synthesized on (100) Si substrate with silicon oxide film by Cu catalyst-driven solid-liquid-solid mechanism (SLS) during annealing process (1080 °C for 30 min under Ar/H2 atmosphere). Micro size Cu pattern fabrication decided whether α-SiNWs can grow or not. Meanwhile, those micro size Cu patterns also controlled the position and density of wires. During the annealing process, Cu pattern reacted with SiO2 to form Cu silicide. More important, a diffusion channel was opened for Si atoms to synthesis α-SiNWs. What is more, the size of α-SiNWs was simply controlled by the annealing time. The length of wire was increased with annealing time. However, the diameter showed the opposite tendency. The room temperature resistivity of the nanowire was about 2.1 × 103 Ω·cm (84 nm diameter and 21 μm length). This simple fabrication method makes application of α-SiNWs become possible.
Keywordsα-SiNWs Cu patterns Annealing time Resistivity
Summary of different SiNW manufacture method
The site and size of nanowires were well controlled.
Need nanofabrication tools.
Metal-catalyzed electroless etching
Template fabrication process was complex.
The site and size of nanowires were well controlled, without any nanofabrication tools.
Complex fabrication process and time-consuming.
Simple and low cost and the quality of SiNW was good.
Novel metal materials were prohibited in clean rooms. Controllability is poor.
Simple and low cost and no metal catalyst is needed.
Controllability is poor. The compatibility with Si-based integration technology was poor.
In bottom-up approach, chemical vapor deposition (CVD) is an important approach to synthesis SiNWs with low-cost and simple fabrication process. And this approach can readily produce extremely small diameter and super long SiNWs (as recorded, the smallest diameter was 1 nm, and the longest was millimeters) [14–16]. Good quality SiNWs are always synthesized through vapor-liquid-solid (VLS) mechanism with the help of Au or other metals in this method . However, those novel materials are prohibited in clean rooms for degrading the electrical and optical properties of semiconductors.
Catalyst free method is put forward to solve pollution problem which brought by novel catalysts in bottom-up approach. Oxide-assisted growth (OAG) method does not require any metal catalyst . Unfortunately, the compatibility with Si-based integration technology is poor in this method. And products are always affected by other residual impurities easily . Room temperature continuous wave laser ablation of Si is another way to synthesis SiNWs without using metal catalyst . Nevertheless, high vacuum is needed. Even in the simple SiO evaporation technique, good size controllability is always hard to realize. Moreover, SiO powder is harmful to health .
New catalysts such as aluminum and copper are researched to open the door of complementary metal oxide semiconductor (CMOS) technology to SiNWs . Aluminum is used to reduce the deep level impurities; it can also be a p-type dopant producing a shallow acceptor in Si. However, the high sensitivity to oxidation makes using aluminum as catalyst method becoming unpractical. Copper is a good conductor of heat and electricity and has been widely used in integrated circuits (ICs) and CMOS processing. So, copper is considered as the suitable catalyst for SiNW growth. The size and site of Si wires were well controlled by copper catalyst in Kayes et al. work . In the works which copper was used as catalyst to synthesis SiNWs, SiH4, Si2H6, or SiCl4 gases were used as Si precursor [22–24].
In this paper, we present a simple and effective method to synthesis SiNWs on SiO2 films by Cu catalyst-driven SLS mechanism during annealing process without using any toxic precursor gases. This method has two advantages. Firstly, the metal contamination of the SiNWs was decreased. Secondly, no toxic precursor gases were used.
One thousand standard cubic centimeters per minute of Ar was used to exclude air in the tube for 10 min after chips were put on quartz boat and transferred into the center of the horizontal furnace.
Scanning electron microscopy (SEM, Hitachi S-4800) and high-resolution transmission electron microscopy (TEM, JEM-2100F operating at 200 Kv) equipped with energy dispersive spectrometer (EDS) were employed for analyzing the morphology and composition of the nanowires. For TEM measurements, Mo grid was used to support nanowires. For FIB etching the root of the wire, a thin layer of Au was evaporated on the surface to protect the wire by electron-beam-induced deposition (EBID). Two-terminal device was used to measurement the resistivity of nanowire . The wire was mechanically removed from the substrate by nano-operator equipped on focused ion beam (FIB) (FEI, QUANTA3D 600FIB System). Then, nanowire was weld on the two electrodes by Pt deposited with assisted electron beam. Finally, the resistivity of the nanowire was measured by Cascade Semi-automatic probe station HP 4156.
Results and Discussion
The diameter of α-SiNW is decreased from 81 to 57 nm in annealing time increasing process. Usually, the length of SiNW depends on their diameter for Gibbs-Thomson effect in vapor-liquid-solid growth using silane as gaseous source and gold as catalyst. The length of SiNW increases when diameter increased for nanowires with diameter under 100 nm. Nevertheless, the result in our experiment shows the inverse conclusion that the diameter decreased with length. Long-time annealing gives more time for Cu atoms diffused into Si substrate, and the volume of silicide catalyst is also decreased. Meanwhile, the diffusion process of Si atoms is continued which made growth of α-SiNW all the time with catalyst particle size change. Therefore, the diameter of α-SiNW is decreased with anneal time.
In conclusion, α-SiNWs are grown directly on SiO2 surface during annealing process in Ar/H2 atmosphere via SLS mechanism without any toxic precursor gases. Cu patterns fabrication is the necessary condition for α-SiNW growth. Meanwhile, Cu patterns are used to control the density and the site of α-SiNWs. What is more, the annealing time is adjustable parameters to control the diameter and length of wire α-SiNWs. The room temperature resistivity of the nanowire is 2.15 × 103 Ω·cm. This new growth method makes α-SiNWs candidate for potential applications in the future.
This work was supported by the National Natural Science Foundation of China (nos. 51505083 and 51505089).
ZY designed the experiments. ZY synthesized the silicon nanowires. KC and ZN conceived the study. ZY, CW, and YC analyzed the SEM data and wrote the initial drafts of the work. All authors discussed the results and commented on the manuscript. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Open AccessThis article is distributed under the terms of the Creative Commons Attribution 4.0 International License (http://creativecommons.org/licenses/by/4.0/), which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.
- Yu P, Wu J, Liu S, et al. (2016) Design and fabrication of silicon nanowires towards efficient solar cells. Nano TodayGoogle Scholar
- Schmidt V, Wittemann JV, Senz S, Gosele U (2009) Silicon nanowires: a review on aspects of their growth and their electrical properties. Adv Mater 21(25–26):2681–2702View ArticleGoogle Scholar
- Peng KQ, Lee ST (2011) Silicon nanowires for photovoltaic solar energy conversion. Adv Mater 23(2):198–215View ArticleGoogle Scholar
- Lu W, Lieber CM (2007) Nanoelectronics from the bottom up. Nat Mater 6(11):841–850. doi:https://doi.org/10.1038/Nmat2028 View ArticleGoogle Scholar
- Wang YL, Wang TY, Da PM, Xu M, Wu H, Zheng GF (2013) Silicon nanowires for biosensing, energy storage, and conversion. Adv Mater 25(37):5177–5195View ArticleGoogle Scholar
- Dasgupta NP, Sun JW, Liu C, Brittman S, Andrews SC, Lim J, Gao HW, Yan RX, Yang PD (2014) 25th anniversary article: semiconductor nanowires synthesis, characterization, and applications. Adv Mater 26(14):2137–2184. doi:https://doi.org/10.1002/adma.201305929 View ArticleGoogle Scholar
- Park I, Li Z, Pisano AP et al (2009) Top-down fabricated silicon nanowire sensors for real-time chemical detection. Nanotechnology 21(1):015501View ArticleGoogle Scholar
- Morton KJ, Nieberg G, Bai S et al (2008) Wafer-scale patterning of sub-40 nm diameter and high aspect ratio (>50: 1) silicon pillar arrays by nanoimprint and etching. Nanotechnology 19(34):345301View ArticleGoogle Scholar
- Huang Z, Fang H, Zhu J (2007) Fabrication of silicon nanowire arrays with controlled diameter, length, and density. Adv Mater 19(5):744–748View ArticleGoogle Scholar
- Huang Z, Geyer N, Werner P et al (2011) Metal-assisted chemical etching of silicon: a review. Adv Mater 23(2):285–308View ArticleGoogle Scholar
- Chang SW, Chuang VP, Boles ST et al (2009) Densely packed arrays of ultra-high-aspect-ratio silicon nanowires fabricated using block-copolymer lithography and metal-assisted etching. Adv Funct Mater 19(15):2495–2500View ArticleGoogle Scholar
- Bai F, Li M, Huang R et al (2012) Template-free fabrication of silicon micropillar/nanowire composite structure by one-step etching. Nanoscale Res Lett 7(1):557View ArticleGoogle Scholar
- Yun SS, Yoo SK, Yang S et al (2008) Volume-producible fabrication of a silicon nanowire via crystalline wet etching of (1 1 0) silicon. J Micromech Microeng 18(9):095017View ArticleGoogle Scholar
- Ma DDD, Lee CS, Au FCK, Tong SY, Lee ST (2003) Small-diameter silicon nanowire surfaces. Science 299(5614):1874–1877. doi:https://doi.org/10.1126/science.1080313 View ArticleGoogle Scholar
- Shi WS, Peng HY, Zheng YF, Wang N, Shang NG, Pan ZW, Lee CS, Lee ST (2000) Synthesis of large areas of highly oriented, very long silicon nanowires. Adv Mater 12(18):1343–1345. doi:https://doi.org/10.1002/1521-4095(200009)12%3A18<1343%3A%3AAid-Adma1343>3.0.Co%3B2-Q View ArticleGoogle Scholar
- Park WI, Zheng GF, Jiang XC, Tian BZ, Lieber CM (2008) Controlled synthesis of millimeter-long silicon nanowires with uniform electronic properties. Nano Lett 8(9):3004–3009. doi:https://doi.org/10.1021/Nl802063q View ArticleGoogle Scholar
- Wang N, Tang YH, Zhang YF, Lee CS, Bello I, Lee ST (1999) Si nanowires grown from silicon oxide. Chem Phys Lett 299(2):237–242. doi:https://doi.org/10.1016/S0009-2614(98)01228-7 View ArticleGoogle Scholar
- Xu XD, Wang YC, Liu ZF, Zhao RG (2007) A new route to large-scale synthesis of silicon nanowires in ultrahigh vacuum. Adv Funct Mater 17(11):1729–1734. doi:https://doi.org/10.1002/adfm.200600658 View ArticleGoogle Scholar
- Kokai F, Inoue S, Hidaka H, Uchiyama K, Takahashi Y, Koshio A (2013) Catalyst-free growth of amorphous silicon nanowires by laser ablation. Appl Phys a-Mater 112(1):1–7. doi:https://doi.org/10.1007/s00339-012-7169-y View ArticleGoogle Scholar
- Behura SK, Yang QQ, Hirose A, Jani O, Mukhopadhyay I (2014) Catalyst-free synthesis of silicon nanowires by oxidation and reduction process. J Mater Sci 49(10):3592–3597View ArticleGoogle Scholar
- Arbiol J, Kalache B, i Cabarrocas PR, et al (2007) Influence of Cu as a catalyst on the properties of silicon nanowires synthesized by the vapour–solid–solid mechanism. Nanotechnology 18(30):305606. doi:https://doi.org/10.1088/0957-4484/18/30/305606
- Kayes BM, Filler MA, Putnam MC, et al (2007) Growth of vertically aligned Si wire arrays over large areas (>1 cm2) with Au and Cu catalysts. Appl Phys Lett 91(10):103110Google Scholar
- Renard VT, Jublot M, Gergaud P, Cherns P, Rouchon D, Chabli A, Jousseaume V (2009) Catalyst preparation for CMOS-compatible silicon nanowire synthesis. Nat Nanotechnol 4(10):654–657. doi:https://doi.org/10.1038/nnano.2009.234 View ArticleGoogle Scholar
- Wen CY, Reuter MC, Tersoff J, Stach EA, Ross FM (2010) Structure, growth kinetics, and ledge flow during vapor-solid-solid growth of copper-catalyzed silicon nanowires. Nano Lett 10(2):514–519. doi:https://doi.org/10.1021/Nl903362y View ArticleGoogle Scholar
- Zeng HJ, Li T, Bartenwerfer M, Fatikow S, Wang YL (2013) In situ SEM electromechanical characterization of nanowire using an electrostatic tensile device. J Phys D Appl Phys 46(30):Artn 305501. doi:https://doi.org/10.1088/0022-3727/46/30/305501 View ArticleGoogle Scholar
- Wen, C. Y,Reuter, M. C.; Tersoff, J.; Stach, E. A.; Ross, F. M. Structure, growth kinetics, and ledge flow during vapor-solid-solid growth of copper-catalyzed silicon nanowires. Nano Lett 2010, 10, 514-519Google Scholar
- Cao Y, Yang G (2012) Vertical or horizontal: understanding nanowire orientation and growth from substrates. J Phys Chem C 116(10):6233–6238View ArticleGoogle Scholar
- Yan HF, Xing YJ, Hang QL, Yu DP, Wang YP, Xu J, Xi ZH, Feng SQ (2000) Growth of amorphous silicon nanowires via a solid–liquid–solid mechanism. Chem Phys Lett 323:224–228View ArticleGoogle Scholar
- Cui Y, Duan XF, Hu JT, Lieber CM (2000) Doping and electrical transport in silicon nanowires. J Phys Chem B 104(22):5213–5216. doi:https://doi.org/10.1021/Jp0009305 View ArticleGoogle Scholar