- Nano Express
- Open Access
Amorphous Silicon Nanowires Grown on Silicon Oxide Film by Annealing
© The Author(s). 2017
Received: 5 April 2017
Accepted: 26 July 2017
Published: 10 August 2017
In this paper, amorphous silicon nanowires (α-SiNWs) were synthesized on (100) Si substrate with silicon oxide film by Cu catalyst-driven solid-liquid-solid mechanism (SLS) during annealing process (1080 °C for 30 min under Ar/H2 atmosphere). Micro size Cu pattern fabrication decided whether α-SiNWs can grow or not. Meanwhile, those micro size Cu patterns also controlled the position and density of wires. During the annealing process, Cu pattern reacted with SiO2 to form Cu silicide. More important, a diffusion channel was opened for Si atoms to synthesis α-SiNWs. What is more, the size of α-SiNWs was simply controlled by the annealing time. The length of wire was increased with annealing time. However, the diameter showed the opposite tendency. The room temperature resistivity of the nanowire was about 2.1 × 103 Ω·cm (84 nm diameter and 21 μm length). This simple fabrication method makes application of α-SiNWs become possible.
Summary of different SiNW manufacture method
The site and size of nanowires were well controlled.
Need nanofabrication tools.
Metal-catalyzed electroless etching
Template fabrication process was complex.
The site and size of nanowires were well controlled, without any nanofabrication tools.
Complex fabrication process and time-consuming.
Simple and low cost and the quality of SiNW was good.
Novel metal materials were prohibited in clean rooms. Controllability is poor.
Simple and low cost and no metal catalyst is needed.
Controllability is poor. The compatibility with Si-based integration technology was poor.
In bottom-up approach, chemical vapor deposition (CVD) is an important approach to synthesis SiNWs with low-cost and simple fabrication process. And this approach can readily produce extremely small diameter and super long SiNWs (as recorded, the smallest diameter was 1 nm, and the longest was millimeters) [14–16]. Good quality SiNWs are always synthesized through vapor-liquid-solid (VLS) mechanism with the help of Au or other metals in this method . However, those novel materials are prohibited in clean rooms for degrading the electrical and optical properties of semiconductors.
Catalyst free method is put forward to solve pollution problem which brought by novel catalysts in bottom-up approach. Oxide-assisted growth (OAG) method does not require any metal catalyst . Unfortunately, the compatibility with Si-based integration technology is poor in this method. And products are always affected by other residual impurities easily . Room temperature continuous wave laser ablation of Si is another way to synthesis SiNWs without using metal catalyst . Nevertheless, high vacuum is needed. Even in the simple SiO evaporation technique, good size controllability is always hard to realize. Moreover, SiO powder is harmful to health .
New catalysts such as aluminum and copper are researched to open the door of complementary metal oxide semiconductor (CMOS) technology to SiNWs . Aluminum is used to reduce the deep level impurities; it can also be a p-type dopant producing a shallow acceptor in Si. However, the high sensitivity to oxidation makes using aluminum as catalyst method becoming unpractical. Copper is a good conductor of heat and electricity and has been widely used in integrated circuits (ICs) and CMOS processing. So, copper is considered as the suitable catalyst for SiNW growth. The size and site of Si wires were well controlled by copper catalyst in Kayes et al. work . In the works which copper was used as catalyst to synthesis SiNWs, SiH4, Si2H6, or SiCl4 gases were used as Si precursor [22–24].
In this paper, we present a simple and effective method to synthesis SiNWs on SiO2 films by Cu catalyst-driven SLS mechanism during annealing process without using any toxic precursor gases. This method has two advantages. Firstly, the metal contamination of the SiNWs was decreased. Secondly, no toxic precursor gases were used.
One thousand standard cubic centimeters per minute of Ar was used to exclude air in the tube for 10 min after chips were put on quartz boat and transferred into the center of the horizontal furnace.
Scanning electron microscopy (SEM, Hitachi S-4800) and high-resolution transmission electron microscopy (TEM, JEM-2100F operating at 200 Kv) equipped with energy dispersive spectrometer (EDS) were employed for analyzing the morphology and composition of the nanowires. For TEM measurements, Mo grid was used to support nanowires. For FIB etching the root of the wire, a thin layer of Au was evaporated on the surface to protect the wire by electron-beam-induced deposition (EBID). Two-terminal device was used to measurement the resistivity of nanowire . The wire was mechanically removed from the substrate by nano-operator equipped on focused ion beam (FIB) (FEI, QUANTA3D 600FIB System). Then, nanowire was weld on the two electrodes by Pt deposited with assisted electron beam. Finally, the resistivity of the nanowire was measured by Cascade Semi-automatic probe station HP 4156.
Results and Discussion
The diameter of α-SiNW is decreased from 81 to 57 nm in annealing time increasing process. Usually, the length of SiNW depends on their diameter for Gibbs-Thomson effect in vapor-liquid-solid growth using silane as gaseous source and gold as catalyst. The length of SiNW increases when diameter increased for nanowires with diameter under 100 nm. Nevertheless, the result in our experiment shows the inverse conclusion that the diameter decreased with length. Long-time annealing gives more time for Cu atoms diffused into Si substrate, and the volume of silicide catalyst is also decreased. Meanwhile, the diffusion process of Si atoms is continued which made growth of α-SiNW all the time with catalyst particle size change. Therefore, the diameter of α-SiNW is decreased with anneal time.
In conclusion, α-SiNWs are grown directly on SiO2 surface during annealing process in Ar/H2 atmosphere via SLS mechanism without any toxic precursor gases. Cu patterns fabrication is the necessary condition for α-SiNW growth. Meanwhile, Cu patterns are used to control the density and the site of α-SiNWs. What is more, the annealing time is adjustable parameters to control the diameter and length of wire α-SiNWs. The room temperature resistivity of the nanowire is 2.15 × 103 Ω·cm. This new growth method makes α-SiNWs candidate for potential applications in the future.
This work was supported by the National Natural Science Foundation of China (nos. 51505083 and 51505089).
ZY designed the experiments. ZY synthesized the silicon nanowires. KC and ZN conceived the study. ZY, CW, and YC analyzed the SEM data and wrote the initial drafts of the work. All authors discussed the results and commented on the manuscript. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
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