Fig. 1
From: The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
Schematic of DG-TFET DRAM cell. This figure shows the schematic of dual-gate TFET (DGTFET) DRAM cell, including Gate1, Gate2, source, drain, and channel. In this design, the source region and drain region are P+ doping and N+ doping, respectively. Gate1 and Gate2 are N+ polysilicon and P+ polysilicon, respectively