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Fig. 2 | Nanoscale Research Letters

Fig. 2

From: The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Fig. 2

Hole concentrations on the surface of the channel after writing operation. This figure shows the variations of hole concentration with the different Gate2 voltages. The cutline is taken at the surface of the device from the source region to the drain region. In this figure, the solid line and dash line represent the hole concentration after writing “1” and writing “0”, respectively

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