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Fig. 5 | Nanoscale Research Letters

Fig. 5

From: The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET

Fig. 5

Recombination rate in DG-TFET DRAM cell after holding “1” when the Gate2 voltage is a 0 V and b −0.5 V; c energy band diagram and d hole concentration after holding “0”. a, b The recombination rate after holding “1” when the Gate2 voltage is set to 0 V and −0.5 V, respectively. c The energy band of device from the source region to drain region. d The hole concentration of the device after holing “0”. The energy band and hole concentration is extracted at the 3 nm below the gate oxide

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