Fig. 9From: The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET a Transient drain currents in the sequence of the operation; b variation of reading current with the holding time. a The transient current of DGTFET DRAM cell during the writing, holding and reading operations. b The variations of reading “1” and reading “0” current with the different holing timesBack to article page