Table 1 Optimized Programming Condition
From: The Programming Optimization of Capacitorless 1T DRAM Based on the Dual-Gate TFET
Operation | V g1 | V g2 | V d | V s |
|---|---|---|---|---|
Writing “1” | 0 V | −1.3 V | 0 V | 0 V |
Writing “0” | 0 V | 1.3 V | 0 V | 0 V |
Holding | 0 V | −0.2 V | 0 V | 0 V |
Reading | 1 V | 0.8 V | 1 V | 0 V |