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Fig. 3 | Nanoscale Research Letters

Fig. 3

From: Study on the Multi-level Resistance-Switching Memory and Memory-State-Dependent Photovoltage in Pt/Nd:SrTiO3 Junctions

Fig. 3

Consecutive RS cycles a from LRS to HRS and b from HRS to LRS. The device was firstly set to LRS (HRS) by a − 5 V (+ 5 V) pulse with 100 ms width and then applied by a + 5 V (− 5 V) pulse with varied pulse widths of 100 ns, 10 μs, and 10 ms, respectively. The corresponding resistance transition from LRS (HRS) to intermediate resistance states or HRS (LRS). c RV hysteresis loops controlled by pulse voltage. The Pt/Nd:STO/In device was firstly set to LRS by a pulse of − 3 V, followed by sweeping the pulse to + 2 V (or + 3, + 4, and + 5 V) and back to − 3 V with 100-ms pulse width. All the resistance was read at 0.1 V

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