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Table 1 Optimized programming condition for DGTFET DRAM

From: The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

Operation

Vg1

Vg2

Vd

Vs

Writing “1”

0 V

− 1.3 V

0 V

0 V

Writing “0”

0 V

1.3 V

0 V

0 V

Holding

0 V

− 0.2 V

0 V

0 V

Reading

0.7 V

0.7 V

1 V

0 V

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