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Table 2 Extracted performance properties of DGTFET DRAM with different spacer dielectrics

From: The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

	Holding time = 100 ns			Holding time = 2 s
	I₁(A/μm)	I₀(A/μm)	I₁/I₀	I₁(A/μm)	I₀(A/μm)	I₁/I₀
S/S/S	2.20 × 10⁻⁷	2.96 × 10⁻¹¹	7.45 × 10³	1.29 × 10⁻⁷	2.51 × 10⁻⁸	5.12
S/H/S	2.20 × 10⁻⁷	2.95 × 10⁻¹¹	7.45 × 10³	1.29 × 10⁻⁷	2.38 × 10⁻⁸	5.43
S/S/H	2.02 × 10⁻⁷	1.40 × 10⁻¹⁴	1.44 × 10⁷	1.29 × 10⁻⁷	6.46 × 10⁻¹²	2.00 × 10⁴
S/H/H	2.01 × 10⁻⁷	1.35 × 10⁻¹⁴	1.49 × 10⁷	1.29 × 10⁻⁷	6.13 × 10⁻¹²	2.11 × 10⁴
H/S/S	1.29 × 10⁻⁹	2.81 × 10⁻¹¹	4.58 × 10¹	9.08 × 10⁻¹⁴	1.29 × 10⁻¹¹	7.07 × 10⁻³
H/H/S	1.29 × 10⁻⁹	2.81 × 10⁻¹¹	4.58 × 10¹	1.53 × 10⁻¹⁴	1.29 × 10⁻¹¹	1.19 × 10⁻³
H/S/H	3.77 × 10⁻⁹	1.21 × 10⁻¹⁴	3.11 × 10⁵	3.04 × 10⁻¹³	1.58 × 10⁻¹⁴	1.92 × 10¹
H/H/H	3.81 × 10⁻⁹	1.21 × 10⁻¹⁴	3.15 × 10⁵	2.52 × 10⁻¹³	1.49 × 10⁻¹⁴	1.69 × 10¹

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