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Table 2 Extracted performance properties of DGTFET DRAM with different spacer dielectrics

From: The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

  Holding time = 100 ns Holding time = 2 s
I1(A/μm) I0(A/μm) I1/I0 I1(A/μm) I0(A/μm) I1/I0
S/S/S 2.20 × 10−7 2.96 × 10−11 7.45 × 103 1.29 × 10−7 2.51 × 10−8 5.12
S/H/S 2.20 × 10−7 2.95 × 10−11 7.45 × 103 1.29 × 10−7 2.38 × 10−8 5.43
S/S/H 2.02 × 10−7 1.40 × 10−14 1.44 × 107 1.29 × 10−7 6.46 × 10−12 2.00 × 104
S/H/H 2.01 × 10−7 1.35 × 10−14 1.49 × 107 1.29 × 10−7 6.13 × 10−12 2.11 × 104
H/S/S 1.29 × 10−9 2.81 × 10−11 4.58 × 101 9.08 × 10−14 1.29 × 10−11 7.07 × 10−3
H/H/S 1.29 × 10−9 2.81 × 10−11 4.58 × 101 1.53 × 10−14 1.29 × 10−11 1.19 × 10−3
H/S/H 3.77 × 10−9 1.21 × 10−14 3.11 × 105 3.04 × 10−13 1.58 × 10−14 1.92 × 101
H/H/H 3.81 × 10−9 1.21 × 10−14 3.15 × 105 2.52 × 10−13 1.49 × 10−14 1.69 × 101