Table 3 Performance properties of various TFET DRAM utilized as DRAM
Device configuration [Reference] | Device size | RT | Reading “0” current |
---|---|---|---|
FD-SOI TFET with intrinsic region [17] | Lg 400 nm; Intrinsic Region Length (Lin) 200 nm | 1.2 μA/μm | |
DG FD-SOI TFET [18] | Lg1 400 nm; Lg2 200 nm; Lin 200 nm | 100 μs~#ms | 50 nA/μm |
DGTFET with front gate [19] | Lg1 400 nm; Lg2 200 nm; Lgap 200 nm | 1.5 s | 0.1 nA/μm |
DGTFET with back gate [20] | Lfront gate 400 nm; Lback gate 200 nm | 170 ms | 0.1 nA/μm |
Prsent work | Lg1 400 nm; Lg2 200 nm; Lgap 50 nm | 10 s | 14fA/μm |