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Table 4 Extracted performance properties of S/S/H with the decreasing of device size

From: The Optimization of Spacer Engineering for Capacitor-Less DRAM Based on the Dual-Gate Tunneling Transistor

  Holding time = 100 ns Holding time = 2 s
I1(A/μm) I0(A/μm) I1/I0 I1(A/μm) I0(A/μm) I1/I0(A/μm)
400/50/200 2.02 × 10−7 1.40 × 10−14 1.44 × 107 1.29 × 10−7 6.46 × 10−12 2.00 × 104
300/50/200 1.78 × 10−7 8.33 × 10−12 2.13 × 104 1.09 × 10−7 3.67 × 10−11 2.97 × 103
200/50/200 1.28 × 10−7 5.23 × 10−11 2.45 × 103 7.99 × 10−8 2.26 × 10−10 3.54 × 102
100/50/200 4.45 × 10− 8 3.06 × 10− 10 1.45 × 102 3.24 × 10− 8 1.17 × 10−9 2.76 × 101
200/50/150 1.36 × 10−7 8.17 × 10−11 1.67 × 103 8.01 × 10−8 5.56 × 10−10 1.44 × 102
200/50/100 1.47 × 10−7 2.41 × 10−10 6.08 × 102 8.22 × 10−8 2.51 × 10−9 3.28 × 101
200/40/150 1.36 × 10−7 8.22 × 10−11 1.65 × 103 8.10 × 10−8 5.57 × 1010 1.45 × 102
200/30/150 1.35 × 10−7 9.00 × 10−11 1.51 × 103 8.11 × 10−8 5.82 × 10−10 1.39 × 102
200/20/150 1.35 × 10−7 9.54 × 10−11 1.41 × 103 8.08 × 10−8 6.24 × 10−10 1.29 × 102
200/10/150 1.35 × 10−7 1.02 × 10−10 1.32 × 103 8.11 × 10−8 1.00 × 10−9 8.10 × 101