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Table 3 PBTS testing results of CL-ES-structured device and BCE-structured device

From: Enhancement of a-IGZO TFT Device Performance Using a Clean Interface Process via Etch-Stopper Nano-layers

T

Bias time

CL-ES

BCE

Vg bias + 30 V

Vg bias + 30 V

Ion (uA)

Ioff (pA)

Vth (V)

SS (V/dec)

Ion (uA)

Ioff (pA)

Vth (V)

SS (V/dec)

RT

0 s

8.29

0.10

− 0.32

0.18

10.32

0.14

1.15

1.70

60 °C

1000 s

8.42

0.00

0.14

0.22

5.50

0.20

5.73

0.93

60 °C

3600 s

7.32

0.19

1.62

0.24

4.26

0.07

6.73

0.84

Shift (1 h–0 h)

− 0.97

0.09

1.94

0.06

− 6.06

− 0.06

5.58

− 0.86

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