Fig. 1From: RTN and Annealing Related to Stress and Temperature in FIND RRAM Arraya 3D illustration of the 2 T FIND RRAM cells implemented by CMOS FinFET technologies and b the circuit schematic of a unit cell for FIND RRAM under read condition is shown, where VSL = VWL = 0.8 V and BL is biased at zeroBack to article page