Fig. 11
From: RTN and Annealing Related to Stress and Temperature in FIND RRAM Array
The on-chip annealing scheme we proposed involves applying − 1 V at BL resulting forward bias and a measured current of 1.5 mA, which heats up and anneals the stressed cell. In the plot, by comparing the cumulative percentage of the normalized current of the cell before and after the process, we can see that the current fluctuation caused by RTN is greatly reduced