High mobility Ge pMOSFETs with amorphous Si passivation: impact of surface orientation

Abstract

We report the amorphous Si passivation of Ge pMOSFETs fabricated on (001)-, (011)-, and (111)-orientated surfaces for advanced CMOS and thin film transistor applications. Amorphous Si passivation of Ge is carried out by magnetron sputtering at room temperature. With the fixed thickness of Si t_Si, (001)-oriented Ge pMOSFETs achieve the higher on-state current I_ON and effective hole mobility μ_eff compared to the devices on other orientations. At an inversion charge density Q_inv of 3.5 × 10¹² cm⁻², Ge(001) transistors with 0.9 nm t_Si demonstrate a peak μ_eff of 278 cm²/V × s, which is 2.97 times higher than the Si universal mobility. With the decreasing of t_Si, I_ON of Ge transistors increases due to the reduction of capacitive effective thickness, but subthreshold swing and leakage floor characteristics are degraded attributed to the increasing of midgap D_it.

Background

Germanium (Ge) has been attracting tremendous research interests for advanced CMOS and thin film transistor applications due to its higher hole mobility and lower thermal budget processing compared to Si [1,2,3,4,5,6]. To achieve the high channel mobility, the surface passivation process leading to a high interface quality is required before gate stack formation. Several surface passivation techniques have been developed to deliver the carrier mobility benefits in Ge metal-oxide-semiconductor field-effect transistors (MOSFETs) [1, 2, 7,8,9,10]. Among these techniques, a silicon (Si) cap passivated on Ge has been the hotspot in recent years, due to its advantages of effective suppressing of interface states and good thermal stability and reliability [11]. Formation of Si passivation cap has been widely studied using chemical vapor deposition (CVD) with precursors of SiH₄ [1], Si₂H₆ [4], Si₃H₈ [12], and E-beam evaporation [13]. Although CVD method could provide the more uniform passivation layer over physical vapor deposition (PVD), its passivation rate has the strong correlation in channel surface orientation and the process temperature. PVD technique could provide the improved passivation rate even at room temperature, which has the advantages of low thermal budget and low cost, making it more suitable for the thin film transistors and back-end-of-line 3D integration applications. In this letter, we fabricated high mobility Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces utilizing amorphous Si passivation by magnetron sputtering. Significantly improved effective hole mobility μ_eff is achieved in Ge transistors compared to the Si universal mobility. Impacts of surface orientation and thickness of amorphous Si t_Si on the boosting effect of amorphous Si passivation on μ_eff are studied.

Methods

Figure 1a shows the key process steps for fabricating Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces. After pre-gate cleaning in diluted HF (1:50) solution, ultrathin amorphous Si passivation layer was deposited on n-Ge substrates by magnetron sputtering at a target power of 50 W. Three passivation durations of 60 s, 80 s, and 100 s were used corresponding to the deposition of 0.5, 0.7, and 0.9 nm t_si, respectively. After that, a 5-nm thick HfO₂ gate dielectric was deposited at 250 °C by atomic layer deposition using TDMAHf and H₂O as precursors of Hf and O, respectively. A 50-nm TaN gate electrode was deposited by reactive sputtering. Next, the gate electrode was patterned and etched, which was followed by BF₂⁺ implantation into source/drain (S/D) regions at 30 KeV with a dose of 1 × 10¹⁵ cm^− 2. Non-self-aligned S/D metals of 15-nm nickel were formed by lift-off process. Finally, rapid thermal annealing at 400 °C was carried out for dopant activation and S/D metallization. Figure 1b shows the cross-sectional schematic of the Ge pMOSFET with Si/SiO₂ interfacial layer (IL). Figure 1c shows top-view microscope image of a fabricated Ge pMOSFET.

Fig. 1

a Process sequence showing the key steps employed to fabricate the Ge pMOSFETs with different t_Si. b Cross-sectional schematic of a Ge pMOSFET with SiO₂ IL. c Top-view microscope image of a fabricated Ge pMOSFET

Figure 2a, b shows the transmission electron microscope (TEM) images of the high-κ/metal gate stack with SiO₂/Si interfacial layer (IL) on Ge(001) channel with t_Si of 0.5 and 0.9 nm, respectively. Insets show the high-resolution TEM (HRTEM) images of the samples. For the device with a t_Si of 0.5 nm, amorphous Si layer was completely oxidized, while for the device with 0.9 nm t_Si, about two Si monolayers remained after the subsequent annealing steps.

Fig. 2

Cross-sectional TEM images of Ge pMOSFET gate stacks with a 0.5 nm t_Si and b 0.9 nm t_Si. HRTEM images in insets show that Si/SiO₂ IL is formed between HfO₂ and Ge channel

Results and discussion

Figure 3a plots the measured I_DS-V_GS and I_G-V_GS curves of the typical Ge pMOSFETs on (001)-, (011)-, and (111)-oriented surfaces with 0.9 nm t_Si, which show the excellent transfer characteristics. All transistors have a gate length L_G of 3 μm and a gate width W of 100 μm. The channel direction is [110] for all the orientations. The I_DS-V_DS curves of the devices measured at different gate overdrive V_GS-V_TH are shown in Fig. 3b. Here, threshold voltage V_TH is defined as the V_GS at I_DS of 10⁻⁷ A/μm. It is observed that Ge(001) pMOSFET achieves the higher drive current I_ON compared to the transistors on (011) and (111) surfaces at the fixed V_GS-V_TH. Later, we will show that this is attributed to the fact that Ge(001) pMOSFETs have a higher effective hole mobility μ_eff in comparison with the devices on the other two surface orientations. We perform a comprehensive comparison of electrical performance for the devices with the fixed t_Si of 0.9 nm, including I_ON, leakage floor I_leak, subthreshold swing (SS), and V_TH characteristics. I_leak is defined as the minimum I_DS at V_DS of − 0.05 V. Figure 4a presents the statistical plot of the I_ON for Ge pMOSFETs on various orientations, and I_ON was defined as I_DS at a V_DS of − 0.5 V and a V_GS-V_TH of − 0.8 V. All the transistors in this plot have the L_G of 3 μm and W of 100 μm. (001)-oriented devices exhibit the improved mean I_ON as compared to those on (011) and (111) orientations, which is attributed to the higher μ_eff. Figure 4b compares the I_leak for the devices, showing that Ge(001) transistors have the lowest I_leak of them, and Ge(011) pMOSFETs have the lower I_leak than (111)-oriented devices. It should be noted that the I_leak is determined by the reverse current of the p⁺/n junction in drain region, which is affected by the background n-type doping concentration in Ge substrate and activation of the implanted p⁺ dopants. The n-type doping concentrations in the wafers with various orientations are not exactly the same. The surface orientation affects the dopant activation rate and recrystallization quality of S/D regions. Furthermore, although the I_G is lower than I_DS before the turn-on of the transistors, it would influence the I_leak. Similarly, (001)-oriented Ge pMOSFETs demonstrate the improved SS characteristics in comparison with other two orientations, which is due to that transistors on (001) surface have the lower midgap density of interface state D_it compared to the other devices. Figure 4d shows that the devices on different orientations have the different V_TH. Based on the results in Fig. 4, it is concluded that, with the fixed t_Si of 0.9 nm, (001)-oriented Ge pMOSFETs obtain the best electrical characteristics.

Fig. 3

a Measured I_DS-V_GS and I_G-V_GS curves of (001)-, (011)-, and (111)-oriented Ge pMOSFETs with 0.9 nm t_Si showing the excellent transfer characteristics. b I_DS-V_DS curves measured at different V_GS-V_TH for the devices

Fig. 4

Comparison of a I_ON, b I_leak, c SS, and d V_TH for (001)-, (011)-, and (111)-oriented Ge pMOSFETs with a t_Si of 0.9 nm

The thicknesses of Si/SiO₂ IL in transistors with 0.9 nm t_Si on different surface orientations are studied by using inversion capacitance C_inv versus V_GS measurement, as shown in Fig. 5. Forward and reverse sweeping measurements exhibit the negligibly small hysteresis in the devices. The transistors exhibit the similar magnitude of C_inv, ~ 1.56 μF/cm², corresponding to the capacitive effective thickness (CET) of 2.2 nm. Figure 5b show the statistical results of saturated C_inv for the devices, which demonstrate the very small difference in C_inv in the transistors on different surface orientations. This indicates that the passivation rate of amorphous Si by magnetron sputtering is independent of the surface orientation. The rule of left-right shifts of the C_inv-V_GS curves is well consistent with that of V_TH for the devices in Fig. 4d, which might be induced by the slightly different doping concentration in different orientation substrates.

Fig. 5

a Comparison of inversion C_inv-V_GS curves among the Ge pMOSFETs with 0.9 nm t_Si on different orientations. Both forward and reverse sweeping are shown. b Statistical plots for the saturated C_inv of the devices showing the negligible differences in C_inv in the inversion regime

Figure 6 compares the mobility characteristics of the transistors with 0.9 nm t_Si on various surface orientations. The μ_eff was extracted using a total resistance slope-based method [14]. Ge(001) pMOSFETs exhibit the much higher channel mobility compared to the devices on (011) and (111) orientations. Transistors on (001) substrate achieve a peak μ_eff of 278 cm²/V·s at an inversion charge density Q_inv of ~ 3.5 × 10¹² cm⁻², which is 2.97 times higher than the Si universal mobility. Surface roughness at the Si/Ge interface and density of interface states (D_it) can affect μ_eff of the devices at high inversion carrier density. It is unlikely that the commercially purchased Ge wafers with various surface orientations have the obvious difference in surface roughness. Therefore, it is speculated that the mobility enhancement in (001)-oriented devices is mainly due to reduced carrier scattering contributed by interface states. In this work, we evaluate the midgap D_it of the devices, and with the fixed t_Si of 0.9 nm, the (001)-oriented Ge pMOSFETs indeed have the lower midgap D_it compared to the other orientations.

Fig. 6

Plot of μ_eff versus Q_inv for Ge pMOSFETs with 0.9 nm t_Si on (001)-, (011)-, and (111)-oriented substrates. Ge(001) pMOSFETs achieve the 2.97 times enhancement in μ_eff at a Q_inv of 3.5 × 10¹² cm⁻² as compared to the Si universal mobility. The μ_eff was extracted using a total resistance slope-based method [17]

The impact of t_Si on the electrical performance of Ge pMOSFETs is also investigated. Figure 7a, b present the measured I_DS-V_GS and I_DS-V_DS curves, respectively, of the (111)-oriented Ge pMOSFETs with t_Si of 0.5, 0.7, and 0.9 nm at a V_DS of − 0.05 and − 0.5 V. The transistors have a L_G of 1.5 μm. It is observed that Ge pMOSFETs with 0.9 nm t_Si exhibit improved transfer characteristics compared to the devices with thinner t_Si, but I_ON of the device decreases with the increasing of t_Si. At V_DS of − 1.5 V and V_GS-V_TH of − 0.8 V, Ge(111) pMOSFET with 0.5 nm t_Si demonstrates a 32% improvement in I_ON compared to the device with 0.9 nm t_Si. Figure 8 plots the statistical results of I_ON, I_leak, SS, and V_TH of the Ge pMOSFETs on (111)-orientation with different t_Si. From Fig. 8a, we see that transistors with 0.5 nm t_Si achieve the improved I_ON in comparison with the devices with thicker t_Si, which is due to the transistor with 0.5 nm t_Si that has a smaller CET, leading to a higher C_inv. It is noticed that I_leak decreases with the increasing of t_Si (Fig. 8b), and transistors with 0.5 nm t_Si has the inferior SS characteristics to those of the devices with 0.7 and 0.9 nm amorphous Si passivation layer (Fig. 8c). This might be due to those transistors with 0.5 nm t_Si having a higher midgap D_it. The relation between SS and midgap D_it of Ge pMOSFET can be expressed by SS = ln(10) ⋅ (kT/q) ⋅ [1 + (C_it + C_d)/C_ox], where C_ox, C_d, and C_it are oxide capacitance, depletion-layer capacitance, and capacitance from interface traps, respectively. C_it can be calculated by q × D_it, were D_it is the interface trap density. Although transistor with 0.5 nm t_Si has the larger C_ox compared to the other two devices, its higher midgap D_it can lead to the inferior SS to the devices with the thicker t_Si. The surface passivation will also affect the I_leak from drain to source. With the sweeping of V_GS from position to negative, the channel transfers from accumulation mode to inversion mode. However, if the D_it is high, some points in channel surface are pinned by the interface traps, and the leakage paths can be formed, increasing I_leak from drain to source. As shown in Fig. 8d, Ge(111) pMOSFETs show the shift of V_TH to negative V_GS direction with the increasing of t_Si, which is attributed to the increased CET. In addition, the density of traps in the lower bandgap half seems to increase for the thinner t_Si, which might lead to the shift of V_TH [2].

Fig. 7

a I_DS-V_GS and I_G-V_GS and b I_DS-V_DS curves of Ge(111) pMOSFETs with various t_Si. Transistor with 0.5 nm t_Si exhibits a 32% improvement in I_ON compared to the device with 0.9 nm t_Si at V_DS of − 1.5 V and V_GS-V_TH of − 0.8 V

Fig. 8

Comparison of a I_ON, b I_leak, c SS, and d V_TH for (111)-oriented Ge pMOSFETs with 0.5, 0.7, and 0.9 nm t_Si showing that transistors with 0.5 nm t_Si have the better I_ON, but worse SS and I_leak characteristics in comparison with devices with thicker t_Si

Figure 9a shows the C_inv as a function of V_GS curves for the Ge pMOSFETs on (111)-oriented surface with t_Si of 0.5, 0.7, and 0.9 nm measured at a frequency of 300 kHz. The CET values in inversion regions are extracted to be 1.8, 1.9, and 2.2 nm for the devices with 0.5, 0.7, and 0.9 nm t_si, respectively. μ_eff as a function of Q_inv characteristics of the devices are extracted and shown in Fig. 9b. The (111)-oriented Ge pMOSFET with 0.7 nm t_si achieves the highest peak mobility of 229 cm²/V s, which is 2.27 times higher compared to the Si universal mobility. It should be noted that the devices with 0.5 nm t_Si exhibit a significantly improved μ_eff over the transistors with thicker t_Si at high Q_inv (e.g. 10¹³ cm⁻²). This also leads to the higher I_ON at high V_GS-V_TH in the devices with 0.5 nm t_Si compared to the devices with 0.7 and 0.9 nm t_Si. The μ_eff at high Q_inv decreases as t_Si increases from 0.5 nm to 0.7~0.9 nm, which is attributed to the fact that the larger surface roughness leads to the stronger surface roughness scattering of the carriers. During the passivation of Ge surface using magnetron sputtering at room temperature, the diffusion of surface atoms is greatly suppressed. So with the increasing of t_Si, the surface roughness is larger, which can be observed from the HRTEM images in Fig. 2.

Fig. 9

a C_inv-V_G characteristics measured at 300 kHz for (111)-oriented devices with 0.5, 0.7, and 0.9 nm t_Si. b μ_eff as a function of Q_inv for Ge pMOSFETs [17]

In Fig. 10, we benchmark the μ_eff of the Ge pMOSFETs in this work with those of the reported relaxed Ge transistors with Si by E-beam evaporation, SiH₄, Si₂H_6, and Si₃H₈ passivation. Compared to the amorphous Si by E-beam evaporation in Ref. [15], Ge pMOSFETs in this work exhibit the significantly improved μ_eff. It is seen that, at the similar CET, Ge pMOSFETs utilizing amorphous Si passivation by magnetron sputtering have the lower μ_eff in comparison with the devices with Si₂H₆ passivation. The process of passivation using amorphous Si needs to be further optimized to enhance the carrier mobility.

Fig. 10

a μ_eff for the Ge pMOSFETs in this work vs. the published results for relaxed Ge pMOSFETs. b, c Benchmarking of μ_eff extracted at Q_inv = 5 × 10¹² and 1 × 10¹³ cm⁻², respectively, of the Ge pMOSFETs with the different CET values [18, 19]

Ge pMOSFETs with the different t_Si on (001)-oriented surface are also characterized. Figure 11a, b illustrate the measured I_DS-V_GS and I_DS-V_DS curves, respectively, of a pair of Ge(001) pMOSFETs with 0.5 and 0.9 nm t_Si. Similar to the (111)-oriented devices, Ge(001) pMOSFET with 0.5 nm t_Si obtains the improvement in I_ON but the degradation in I_leak compared to the transistor with 0.9 nm t_Si.

Fig. 11

a Measured I_DS-V_GS and I_G-V_GS curves of (001)-oriented Ge pMOSFETs with 0.5 and 0.9 nm t_Si. b I_DS-V_GS curves of the devices

The midgap D_it characteristics of Ge pMOSFETs are studied by the method in [16], and values of D_it are calculated by D_it = [SSlog(e)/(kT/q) − 1]C_G/q, [16] where q is the electron charge, k is Boltzmann’s constant, T is the absolute temperature, and C_G is the measured gate capacitance per unit area. Figure 12 shows D_it as a function of the thickness of amorphous Si with various Ge surface orientations. For (111)-oriented surface, a device with 0.7-nm t_si has the lowest D_it value. With the 0.9 nm t_Si, (001)-oriented device has the lower D_it compared to the transistors on other orientations.

Fig. 12

D_it versus the thickness of amorphous Si with various Ge surface orientations

Finally, we compare the key electrical characteristics of Ge pMOSFETs on the different orientations in Table 1. With a fixed t_Si, Ge(001) pMOSFET has the improved electrical performance compared to the other two orientations. The drive current can be enhanced by reducing the t_Si from 0.9 nm to 0.5 nm, which is due to that the thinner t_Si provides a significantly reduced CET without causing degradation in μ_eff.

Table 1 Key electrical performance of Ge pMOSFETs on the different orientations

Conclusions

Ge pMOSFET passivated by amorphous Si are demonstrated on (001)-, (011)-, and (111)-oriented substrate. With a t_Si of 0.9 nm, the improved I_ON and SS characteristics are obtained in (001)-oriented Ge pMOSFETs in comparison with the devices on (011) and (111) orientations, due to the higher μ_eff and lower midgap D_it. Ge(001) pMOSFETs with 0.9 nm t_Si achieve a peak mobility of 278 cm²/V s at a Q_inv of 3.5 × 10¹² cm⁻², which is 2.97 times higher than the Si universal mobility. It is demonstrated that I_ON of the devices is improved with the decreasing of t_Si due to the reduction of CET. But Ge pMOSFETs with thicker t_Si exhibit the superior subthreshold swing and leakage floor, owing to that midgap D_it can be reduced by increasing t_Si.