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Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer
Nanoscale Research Letters volume 14, Article number: 38 (2019)
An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. N-buried layer is introduced under P-well to provide a low-resistance conduction path and reduce the resistance of the channel region significantly. Enhanced dual-gate structure is formed by N-buried layer while avoiding the vertical punch-through breakdown in off-state. Partial P-buried layer with optimized length is adopted under the N-drift region to extend vertical depletion region and relax the electric field peak in off-state, which enhances breakdown voltage (BV) with low drift region resistance. For the LDMOS with enhanced dual-gate and partial P-buried layer, the result shows that Ron,sp is 8.5 mΩ·mm2 while BV is 43 V.
With the increase of demand for more complex and faster logic function in analog power IC, it is significant to improve the performance of the lateral double-diffused metal-oxide-semiconductor transistor (LDMOS), specially minimizing specific on-resistance (Ron,sp) and maximizing off-state breakdown voltage (BV) [1,2,3,4,5,6,7,8,9]. Most developed technologies focus on the drift region optimizing to improve the trade-off of Ron,sp vs. BV for LDMOS devices [10,11,12,13,14,15,16,17,18,19,20]. In our previous work, the LDMOS with ultra-shallow trench isolation (USTI) was proposed . The depth and corner angel of USTI were optimized to achieve best-in-class performance. However, for the low voltage LDMOS, the drift region is losing domination in Ron,sp and the contribution of the channel region cannot be ignored.
In this work, a novel ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer is investigated. The physical models IMPACT.I, BGN, CONMOB, FLDMOB, SRH, and SRFMOB are used in numerical simulation. On-resistance analytical model is proposed to provide an in-depth insight into the relationship between the drift region resistance and the channel region resistance. Based on the model, N-buried layer and partial P-buried layer are optimized to achieve low Ron,sp and high BV.
Results and Discussion
Figure 1a shows the schematic cross-section of ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer. The LDMOS features the dual-gate with N-buried layer and the partial P-buried layer which contributes to reduce Ron,sp and enhance BV, respectively. In the channel region, the enhanced dual-gate is formed by trench gate and highly doped N-buried layer. Compare to conventional dual-gate structure, N-buried layer significantly reduce the resistance of the channel region by provide a low on-resistance conduction path under P-well in the on-state. In the drift region, the partial P-buried layer with high doping concentration is introduced under the N-drift region to enhance BV while maintaining low Ron,sp. The partial P-buried layer helps to reduce the vertical electric field in the off-state without breaking charge balance in the drift region. The key size of the novel device is listed in Table 1.
Figure 1b shows the schematic equivalent on-resistance model for the proposed LDMOS. The total on-resistance is considered as the resistance of the drift region (Rd) and the resistance of the channel region (Rc) in series. In the channel region, surface channel conduction path parallels the trench channel conduction path. Thus, Rc is equal to (Rchs + Racc)//(Rcht + Rnb), where Rchs, Racc, Rcht, and Rnb are the resistances of the surface-gate channel, the accumulation region, the trench gate channel, and the N-buried layer, respectively. Based on the proposed on-resistance model, the reduction of Rc would achieve by decreasing Rnb without affecting the other performances, because the other resistances are mainly determinate by the process technology, operation voltage, and threshold voltage. The Rd has been reduced by introducing P-buried layer under N-drift region to enhance the Reduce Surface-field (RESURF) effect in our previous work. In this work, the partial P-buried layer is adopted to improve the BV while maintaining the low Rd.
Aiming at the reduction of Rc, the N-buried layer with high doping concentration is introduced under P-well. Figure 2 shows numerical and analytical Rc as functions of the doping concentration of the N-buried layer (Nnb) with single-gate and dual-gate. It is indicated that the dual-gate structure helps to reduce Rc compared with the single-gate. When Nnb = Nd = 5.5 × 1016 cm−3, Rc is 110 mΩ. According to the on-resistance model, Rnb is the main contributor to Rc. And then, the Rnb is desired to decrease with the aim of smaller Rc. As shown in Fig. 2a, Rc is reduced with Nnb increasing. When Nnb = 1.35 × 1017 cm−3, Rc is reduced to 85 mΩ. However, Fig. 2 also shows that Nnb would be limited by punch-through breakdown. Because of adding trench gate, Rc is decreased firstly by 34% with Nnb = Nd = 5.5 × 1016 cm−3. As Nnb increases, Rc continuously decreases. With optimized Nnb = 1.05 × 1017 cm−3, Rc is decreased by 45% at last. When Nnb > 1.05 × 1017 cm−3, punch-through breakdown will happen in P-well. The analytical result of Ron,sp shown in Fig. 2 indicates that the proposed model provides a good fitting with numerical simulation results. Therefore, the model is believable to guide the optimization design.
Figure 3a shows numerical BV as a function of Nnb with different doping concentration of P-well (Npwell). Nnb has an effect on not only the Rc, but also the BV. For a given Npwell, BV keeps unchanged at small Nnb, and then decreases with Nnb increasing. When Nnb increases to 1.2 × 1017 cm−3, BV starts to drop with Npwell = 2 × 1017 cm−3. The drop of BV is ascribed to punch-through breakdown in the P-well region as shown in Fig. 3b. As drain voltage increases, the depletion region in P-well extends to the source. When the depletion region attacks the N+/P-well junction, the punch-through breakdown occurs. For a large Npwell, the depletion mainly extends to the drift region, and the punch-through breakdown is avoided without degrading the BV. Although P-well with high doping concentration benefits to avoid the punch-through breakdown, it would enhance the threshold voltage. Thus, Npwell of 2 × 1017 cm−3 is chosen with consideration to threshold voltage and the trade-off between the BV and Ron,sp.
In order to achieve low Rd and high BV, partial P-buried layer is introduced under the N-drift region. Figure 4a shows BV as a function of ΔLpb with different Npb. For a given Npb, as ΔLpb increases, BV increases and then decreases slightly. When ΔLpb = 0.1 μm, Npb = 1 × 1017 cm−3, BV reaches the maximum value 43 V. The insert shows the equipotential contour profile with Npb = 1 × 1017 cm−3. It is indicated that the equipotential contour in the partial P-buried layer structure extends more to substrate with comparison to full P-buried layer. Figure 4b shows electric field distribution at the surface and the P-buried/N-drift junction interface. For optimized conventional LDMOS, the breakdown occurs usually at the N-drift/P-buried interface. For the proposed LDMOS, the junction of N-drift/P-sub replaces the junction of N-drift/P-buried to relax the vertical electric field and extend depletion region, which results in a higher BV while maintaining low Rd.
Charge balance between N-drift and partial P-buried layer is required to achieve high BV. Figure 5a shows that numerical and analytical BV and Ron,sp as functions of the doping concentration of the P-buried (Npb) for different Nd. For a given Nd, BV has a maximum value with varied Npb, and the maximum of BV increases with the decrease of Nd. However, Ron,sp can be increased as the Nd decreasing. Due to BV required higher than 40 V, the Nd = 5.5 × 1016 cm−3 and Npb = 1 × 1017 cm−3 are chosen. Figure 5b shows numerical and analytical BV and Ron,sp as functions of the thickness of the STI layer (Tsti). Tsti has strong impact on BV and Ron,sp, and it should be designed and optimized carefully as well as our previous work . For Tsti < 0.3 μm, the breakdown point under the edge of poly field plate has a high electric field peak. As Tsti increases, the electric field peak is relaxed, and then BV increases. For Tsti = 0.3 μm, BV of 43 V is obtained. For Tsti ≥ 0.3 μm, the electric field peak under the edge of poly field plate is enough low, as a result, the breakdown point transfers to P/N junction under the drain side. As Tsti increases, BV increases and then saturates.
Figure 6 shows the benchmark of existing Bipolar-CMOS-DMOS (BCD) technologies and the proposed LDMOS. Apparently, the process technology for proposed LDMOS is compatible with our developed BCD technology which achieved the best-in-class performance of LDMOS. In the fabrication process for the proposed LDMOS, N-buried layer could share the same mask with P-well. For the proposed LDMOS, Ron,sp is 8.5 mΩ·mm2 while BV = 43 V, which is reduced by about 37% compared with our previous work.
A novel ultra-low specific on-resistance LDMOS with enhanced dual-gate and partial P-buried layer is proposed and investigated by numerical simulation in this paper. N-buried layer with high doping concentration is utilized to achieve enhanced dual-gate with reducing Rc. Partial P-buried layer is introduced under the N-drift region to enhance BV with keeping charge balance. The fabrication process of the LDMOS in this work is compatible with the existing BCD technology reported in our previous work. The result shows that the Ron,sp of the proposed LDMOS is reduced by 37% at BV of 43 V compared with previous work. With the semiconductor processing technology going to nanometer level, the Ron,sp can reduce further with channel length decrease.
Lateral double-diffused metal-oxide-semiconductor transistor
- R on,sp :
Ultra-shallow trench isolation
Disney D, Chan W, Lam R, Blattner R, Ma S, Seng W, Chen J-W, Cornell M, Williams R (2008) 60 V lateral trench MOSFET in 0.35 μm technology. Proc ISPSD:24–27. https://doi.org/10.1109/ISPSD.2008.4538888
Erlbacher T, Bauer AJ, Frey L (2010) Reduced on resistance in LDMOS devices by integrating trench gates into planar technology. IEEE Electron Device Lett. 31(5):464–466. https://doi.org/10.1109/LED.2010.2043049
Shimamoto S, Yanagida Y, Shirakawa S, Miyakoshi K, Imai T, Oshima T, Sakano J, Wada S (2011) High performance Pch-LDMOS transistors in wide range voltage from 35V to 200V SOI LDMOS platform technology. Proc ISPSD:44–47. https://doi.org/10.1109/ISPSD.2011.5890786
Fujii H, Tokumitsu S, Mori T, Yamashita T, Maruyama T, Maruyama T, Maruyama Y, Nishimoto S, Arie H, Kubi S, Ipposhi T (2017) A 90nm bulk BiCDMOS platform technology with 15–80V LD-MOSFETs for automotive applications. Proc ISPSD:73–76. https://doi.org/10.23919/ISPSD.2017.7988896.
Huang T-Y, Liao W-Y, Yang C-Y, Huang C-H, Yeh W-CV, Huang C-F, Lo K-H, Chiu C-W, Kao T-C, Su H-D, Chang K-C (2014) 0.18 um BCD technology with best-in-class LDMOS from 6 V to 45 V. Proc ISPSD:179–181. https://doi.org/10.1109/ISPSD.2014.6856005
Lee K, Jeon H, Cho B, Cho J, Pang Y-S, Moon J, Kwon S, Hébert F, Lee J, Lee T (2013) 0.35 μm, 30V fully isolated and low-Ron nLDMOS for DC-DC applications. Proc ISPSD:163–166. https://doi.org/10.1109/ISPSD.2013.6694454
Jang J, Cho K-H, Jang D, Kim M, Yoon C, Park J, Oh H, Kim C, Ko H, Lee K, Yi S (2013) Interdigitated LDMOS. Proc ISPSD:245–248. https://doi.org/10.1109/ISPSD.2013.6694462.
Roggero R, Croce G, Gattari P, Castellana E, Molfese A, Marchesi G, Atzeni L, Buran C, Paleari A, Ballarin G, Manzini S, Alagi F, Pizzo G (2013) BCD8sP: an advanced 0.16 μm technology platform with state of the art power devices. Proc ISPSD:361–364. https://doi.org/10.1109/ISPSD.2013.669442.
Ko K-S, Lee S-H, Kim D-H, Eum J-N, Park S-K, Cho I-W, Kim J-H, Yoo K-D (2013) HB1340 - advanced 0.13 um BCDMOS technology of complimentary LDMOS including fully isolated transistors. Proc ISPSD:159–162. https://doi.org/10.1109/ISPSD.2013.6694453.
van der Pol JA, Ludikhuize AW, Huizing HGA, vanVelzen B, Hueting RJE, Mom JF, van Lijnschoten G, Hessels GJJ, Hooghoudt EF, van Huizen R, Swanenberg MJ, Egbers JHHA, van den Elshout F, Koning JJ, Schligtenhorst H, Soeteman J (2000) A-BCD: an economic 100 V RESURF silicon-on-insulator BCD technology for consumer and automotive applications. Proc ISPSD:327–330. https://doi.org/10.1109/ISPSD.2000.856836
Wei J, Luo X, Ma D, Wu J, Li Z, Zhang B (2016) Accumulation mode triple gate SOI LDMOS with ultralow on-resistance and enhanced transconductance. Proc ISPSD:171–174. https://doi.org/10.1109/ISPSD.2016.7520805
Ge W, Luo X, Wu J, Lv M, Wei J, Ma D, Deng G, Cui W, Yang YH, Zhu KF (2017) Ultra-low on-resistance LDMOS with multi-plane electron accumulation layers. IEEE Electron Device Lett. 38(7):910–913. https://doi.org/10.1109/LED.2017.2701354
Guo Y, Yao J, Zhang B, Lin H, Zhang C (2015) Variation of lateral width technique in SOI high-voltage lateral double-diffused metal–oxide–semiconductor transistors using high-k dielectric. IEEE Electron Device Lett. 36(3):262–264. https://doi.org/10.1109/LED.2015.2393913
Duan B, Yang Y, Zhang B (2009) New superjunction LDMOS with N-type charges’ compensation layer. IEEE Electron Device Lett 30(3):305–307. https://doi.org/10.1109/LED.2009.2012396
Fujishima N, Sugi A, Kajiwara S, Matsubara K, Nagayasu Y, Salama CAT (2002) A high-density low on-resistance trench lateral power MOSFET with a trench bottom source contact. IEEE Trans. Electron Devices 49(8):1462–1468. https://doi.org/10.1109/TED.2002.801434
Xia C, Cheng X, Wang Z, Xu D, Cao D, Zheng L, Shen L, Yu Y, Shen D (2014) Improvement of SOI trench LDMOS performance with double vertical metal field plate. IEEE Trans Electron Devices 61(10):3477–3482. https://doi.org/10.1109/TED.2014.2349553
Iqbal MM-H, Udrea F, Napoli E (2009) On the static performance of the RESURF LDMOSFETS for power ICs. Proc ISPSD:247–250. https://doi.org/10.1109/ISPSD.2009.5158048.
Yoo A, Ng JCW, Sin JKO, Ng WT (2010) High performance CMOS-compatible super-junction FINFETs for sub-100 V applications. IEDM Tech Dig:20.7.1–20.7.4. https://doi.org/10.1109/IEDM.2010.5703402
Nitta T, Yanagi S, Miyajima T, Furuya K, Otsu Y, Onoda H, Hatasako K (2006) Wide voltage power device implementation in 0.25 μm SOI BiC-DMOS. Proc ISPSD:1–4. https://doi.org/10.1109/ISPSD.2006.1666141
Yamaguchi H, Urakami Y, Sakakibara J (2006) Breakthrough of on-resistance Si limit by super 3D MOSFET under 100 V breakdown voltage. Proc ISPSD:1–4. https://doi.org/10.1109/ISPSD.2006.1666071
Jin F, Liu D, Xing J, Yang X, Yang J, Qian W, Yue W, Wang P, Qiao M, Zhang B (2017) Best-in-class LDMOS with ultra-shallow trench isolation and p-buried layer from 18V to 40V in 0.18 μm BCD technology. Proc ISPSD:295–298. https://doi.org/10.23919/ISPSD.2017.7988962
This work was supported in part by the National Natural Science Foundation of China under Contract 61674027, in part by the China Postdoctoral Science Foundation Funded Project under Grant 2017 M612942, and in part by the Natural Science Foundation of Guangdong Province under Grant 2016A030311022 and 2018A030310015, in part by the Applied Fundamental Research Project of Sichuan Province under Grant 18YYJC0482, and in part by the Fundamental Research Funds for the Central Universities under Grant ZYGX2016J210.
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Wang, Z., Yuan, Z., Zhou, X. et al. Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer. Nanoscale Res Lett 14, 38 (2019). https://doi.org/10.1186/s11671-019-2866-5
- Enhanced dual-gate
- Lateral double-diffused metal-oxide-semiconductor transistor (LDMOS)
- Partial buried layer
- Specific on-resistance