Table 1 Parameter selection for RGUC FET in TCAD simulation
Parameters | Values |
---|---|
Body width (W) | 6 nm |
Vertical body thickness (tbv) | 6 nm |
Horizontal body thickness (tbh) | 6 nm |
Spacer thickness between S/D region (tsp) | 0.5 to 4 nm |
Vertical length of the gate (tgate) | 8 to 16 nm |
Gate oxide layer thickness (tox) | 1 nm |
Extension height of spacer between S/D region (hex) | 0 to 10 nm |
Inner height of spacer in the recessed region (hin) | 3 to 10 nm |
Doping concentration (ND) | 1 × 1017 cm−3 to 2 × 1018 cm−3 |
Drain-source voltage (VDS) | 0 to 1.0 V |
Gate-source voltage (VGS) | 0.4 to 1.0 V |