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Enhanced Reliability of a-IGZO TFTs with a Reduced Feature Size and a Clean Etch-Stopper Layer Structure
Nanoscale Research Letters volume 14, Article number: 165 (2019)
The effects of diffuse Cu+ in amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on the microstructure and performance during a clean etch stopper (CL-ES) process and a back channel etch (BCE) process are investigated and compared. The CL-ES layer formed with a clean component, as verified by TOF-SIMS, can protect the a-IGZO layer from the S/D etchant and prevent Cu+ diffusion, which helps reduce the number of accepter-like defects and improve the reliability of the TFTs. The fabricated CL-ES-structured TFTs have a superior output stability (final Ids/initial Ids = 82.2 %) compared to that of the BCE-structured TFTs (53.5%) because they have a better initial SS value (0.09 V/dec vs 0.46 V/dec), and a better final SS value (0.16 V/dec vs 0.24 V/dec) after the high current stress (HCS) evaluation. In particular, the variation in the threshold voltages has a large difference (3.5 V for the CL-ES TFTs and 7.2 V for the BCE TFTs), which means that the CL-ES-structured TFTs have a higher reliability than the BCE-structured TFTs. Therefore, the CL-ES process is expected to promote the widespread application of a-IGZO technology in the semiconductor industry.
Recently, display products have emphasized not only large areas and high resolutions, but also aesthetically pleasing exterior designs [1,2,3]. Narrow bezels have been adopted as one of the vital features for this design emphasis . To realize this, it is essential to integrate the main circuits that drive the display into the panel. Gate drive IC on array (GOA) is a relatively simple and commonly used method, where the gate signal enters the panel one line after another and the Von moves sequentially each time. GOA has multiple advantages, such as decreased cost (elimination of the G-IC costs, removal of the G-IC bonding process, increased glass substrate utilization, etc.) and aesthetic effect (narrow bezels or borderless devices) . Unlike individual pixel TFTs, however, GOA TFTs require more stringent reliability conditions to achieve a higher output current and longer on-time performance. With the recently increasing market demands for high-resolution products, reliability enhancement of the GOA performance has become urgent and necessary .
Amorphous indium-gallium-zinc-oxide (a-IGZO) is widely used in the display industry due to its high saturation electron mobility (5~10 cm2/V s) and low off-current (< 1 pA) [7, 8]. The back channel etch (BCE) technology is commonly used for the production of TFTs in industry [9, 10]. BCE-structured a-IGZO TFTs have satisfactory characteristics for individual pixel TFTs and the size reduction of GOA TFTs. However, some key TFT characteristics, particularly the output current stability, cannot satisfy the high current stress (HCS) environment required for GOA TFTs [11,12,13], mainly due to two features of the BCE process . The first is that the surface of an a-IGZO film (back channel of a-IGZO TFT) is exposed to S/D etchants, which traditionally consist of HNO3, H3PO4, and CH3COOH, that have a fast etching rate that is not controllable for a-IGZO films . A mild H2O2-based etchant with stable etching and minimal damage to the a-IGZO films may be used for the S/D electrode (Cu metal) etching, but damage to the surface of the a-IGZO film is still inevitable . Second, the direct contact of the S/D metal (Mo/Cu/Mo) with the a-IGZO film may contaminate the TFT back channel . Fortunately, a clean etch stopper (CL-ES) process, which is less complicated and costly and minimizes contamination, can be used to fabricate a-IGZO-based TFTs with improved uniformity and stability for large-area displays . Although the CL-ES-structured TFT shows an improved performance, the questions of how the etchant will react with a-IGZO film and how Cu+ diffusion into a-IGZO films affects the microstructure and performance of the devices remain unclear.
In this study, a-IGZO GOA TFTs with a reduced feature size and clean back channel structure were fabricated via a CL-ES process by batch etching of multilayer a-IGZO/Mo/Cu/Mo. Moreover, the influence of the etchant and Cu+ diffusion on the microstructure and performance of CL-ES-structured a-IGZO GOA TFT devices are studied and compared with those of BCE-structured a-IGZO GOA TFT devices. More importantly, the etch stopper layer of the CL-ES device serves as the S/D etchant protection layer as well as the Cu+ diffusion barrier layer, which helps to reduce the amount of defects and improve the reliability of the high current stress reliability, SS values, high current stress and threshold voltage variations, etc. Therefore, this work provides direct evidence and an insightful demonstration that the improved performance of CL-ES-structured TFTs is highly correlated with its CL-ES structure and its clean components and confirms that the CL-ES process might be an efficient route for the mass production of displays with satisfactory performances.
Fabrication of a-IGZO GOA TFTs
The CL-ES-structured a-IGZO TFT devices were fabricated via a modified five-step CL-ES process (Fig. 1), as reported in our previous work . First, the gate electrode was formed with Mo/Cu metal and the gate insulator was deposited with a SiNx/SiOx (3000 Å/1000 Å) double layer using PECVD at 340 °C. Second, an a-IGZO film of 300 Å was deposited using DC magnetron reactive sputtering at room temperature with a partial pressure of oxygen of 15%. An etch stopper layer (SiOx, ESL) of 1000 Å was deposited using PECVD at 240 °C and reactively etched by CF4 plasma for patterning, using the active photolithography mask of the BCE process as the etch mask. For this step, the a-IGZO film under the ES layer patterns was protected from exposure to the CF4 plasma, while the rest of the a-IGZO film, not protected by the ES layer patterns, was not etched either but was converted into a conductive film. Third, the source-drain (S/D) electrodes (Mo/Cu/Mo triple layers) were sputter-deposited and etched using an H2O2 etchant containing 0.2 wt% of a fluoride additive, with the S/D photolithography mask and the ES layer pattern serving as the etch mask. Fourth, a passivation layer of 3000 Å was deposited. The subsequent processes were similar to those of a typical TFT LCD backplane fabrication.
For comparison, BCE-structured a-IGZO TFT devices were fabricated using the conventional BCE process and the same BCE mask.
The morphologies, microstructures, and compositions of the samples were characterized using SEM (Camscan Mx2600FE), X-ray photoelectron spectroscopy (XPS, PHI Quantera II), and time-of-flight secondary ion mass spectrometry (IONTOF, TOF-SIMS 5). Electric measurements were carried out using a semiconductor characteristic analyzer (Keysight 4082A) in a dark environment and at 60 °C. For simplicity, the HCS reliability was evaluated for over 1000 s with Vgs at 25 V and Vds at 25 V. During the evaluation, the state of the GOA TFT was monitored by measuring the Ids current at 1-s intervals, and the trend of the Ids current was analyzed. The Id-Vg transfer characteristics were also monitored at 100-s intervals.
Results and Discussion
The GOA TFT device, containing TFT channels and gate, drain, and source components, as manufactured by the CL-ES process, is shown in Fig. 2. To accurately measure each TFT characteristic, all the TFTs were disconnected using a laser, thus becoming independent, so that the gate, source, and drain could not share a node with any other TFT. As marked by the red line in Fig. 2, this TFT has a multichannel and separated GOA structural design, with a channel width and length of 120 μm and 10 μm, respectively, for convenience of the electrical measurements. This TFT is also designed to have an average level of current flow to the individual TFT channels by placing a floating piece of metal (located in the middle of the channels), which integrates each channel. Before the HCS reliability evaluation, the separated operation reliability is confirmed first by evaluating the electrical interference of the TFT of interest from the other peripheral TFTs. In this case, the Ioff noise current of the separated GOA TFTs is measured to be 3 pA (insert curve in Fig. 2), confirming that there is no electrical interference from the other GOA constituent devices in the vicinity.
Several feature sizes of the CL-ES-structured TFTs and BCE-structured TFTs are measured and compared. For the CL-ES-structured TFTs (Fig. 3a), the width and length are 4 μm and 6 μm, respectively, similar to those of the BCE-structured a-IGZO TFTs in Fig. 3b. Generally, the BCE process is desirable for oxide TFT manufacturing due to its small feature size. Therefore, the obtained CL-ES-structured TFTs show a decreased feature size and an integration degree as high as the BCE-structured TFTs. Moreover, the cross-sectional size of the CL-ES-structured TFTs is similar to that of the BCE-structured TFTs (Fig. 3c, d), while the CL-ES-structured TFTs show a distinct ES layer that is not observed in the BCE TFTs. The CL-ES process primarily forms ES patterns, while the batch etching process on multilayered a-IGZO/Mo/Cu/Mo can be carried out with similar masks for the active patterns and source-drain electrodes as those in the BCE process. Therefore, except for the ES patterns, the number of photolithographic masks used in the CL-ES process is the same as for the BCE process. This CL-ES process can avoid the increased number of masks of the conventional ESL process and has a reduced feature size, making it economically viable for mass production. In addition, without using the half tone exposure, a process simplification procedure conventionally used in the TFT LCD industry, the process complication and the manufacturing cost are both reduced.
To further observe the surface defects of the BCE-structured TFTs during the BCE fabrication process, the surface composition of a-IGZO films before annealing (sample 1), after annealing (sample 2), and after exposure to the H2O2 Cu etchant (sample 3) is studied via XPS. In the fully scanned spectra of a-IGZO films (Fig. 4a–c), peaks for In, Ga, Zn, O, and C elements exist during the BCE fabrication process. As shown in Fig. 4d, although the BCE-structured TFT shows no significant change in the composition of the a-IGZO films before annealing (sample 1) and after annealing at 330 °C for 1 h (sample 2), significant changes are observed after exposure to wet chemicals (sample 3). In particular, zinc, which has a relatively low binding energy with oxygen, is found to be 4.82% in sample 1 and 5.42% in sample 2, but it has decreased to 3.16% in sample 3. Indium has minimal variation in the compositions among the different processes, and the relative percentage change of Zn with respect to In is tremendous, namely, 44.1%, 46.0%, and 27.6% for samples 1, 2, and 3, respectively. This is similar for gallium, which also has a strong binding affinity with oxygen. In other words, during the wet etching process, undesired defects, including a substantial loss of Zn and Ga, occurred on the exposed back surface of the oxide semiconductor. The reasons for this phenomenon may be related to their different binding energies to oxygen and the different molecular structures of the a-IGZO film .
It is well known that the chemical resistance of a-IGZO films to acidic etchants is very weak . In particular, the abrupt loss of Zn, which is believed to determine the molecular structure of a-IGZO, causes a weakening of the surface structure of the a-IGZO films. In addition, the reduction of Ga, which suppresses carrier generation via its strong binding energy with oxygen, may increase the probability of developing oxygen vacancies [Vo] . Therefore, BCE-structured GOA TFTs cannot avoid etching damage to the TFT back channel, even in a relatively mild H2O2-based Cu etchant.
To confirm the protection of the ES layer, the composition of the a-IGZO TFT channel region is studied by using TOF-SIMS for samples prepared by the BCE and CL-ES (clean etch stopper) processes (Fig. 5). Since Cu+ in the a-IGZO film can produce accepter-type defects and trap electrons, the a-IGZO TFT channel must be clean to enhance the electrical stability. As observed, the Cu+ peak detected in the BCE sample is 20 times greater than that of the CL-ES sample. Moreover, the detection region of Cu+ overlaps with the detection region of Zn+ and Ga+ to a great extent (Fig. 5a). These results indicated that the a-IGZO films in the BCE-structured TFTs are contaminated by Cu+ due to the direct contact of the a-IGZO film in the TFT back channel region with the Cu metal. For the CL-ES-structured TFTs (Fig. 5b), Cu+ is only detected in the ES region, indicating that direct contact of the a-IGZO TFT channel region with the Cu metal is avoided. Surprisingly, a considerable amount of Zn+ appears in the ESL. The diffused Zn+ is caused by the higher pretreatment plasma conditions and pressure conditions during ESL deposition. Therefore, the ES layer in CL-ES-structured TFTs is essential to improve the electrical stability by avoiding surface damage to and contamination of the a-IGZO films.
The high current stress (HCS) evaluation for the CL-ES- and BCE-structured GOA a-IGZO TFTs is shown in Fig. 6a. For the same feature sizes, the initial Ids current of the CL-ES-structured TFT is 429 μA, which is higher than that of the BCE-structured TFT (343 μA). After the HCS evaluation for 1000 s, the Ids current of the CL-ES-structured TFT is 352 μA, approximately 82.2 % of its initial value. In contrast, the Ids residual current of the BCE-structured TFT has decreased to 183 μA and only maintains 53.5% of its initial value. Furthermore, as evaluated by extrapolation (Fig. 6b), the Ids residual current of the CL-ES-structured TFT is expected to be 302.6 μA, maintaining 70.5% of its initial value after 10,000 s. For the BCE-structured TFT, the Ids residual current sharply decreases to 111.7 μA, maintaining only 33.7% of its initial value. Therefore, under the same output characteristics, the degree of integration for the GOA TFT fabricated via the CL-ES process can be increased by as much as 271% compared to that of the BCE process.
Additionally, the I-V transfer characteristics of both CL-ES- and BCE-structured GOA TFTs during the HCS reliability evaluation are also measured (Fig. 7 and Table 1). For CL-ES-structured TFT (Fig. 7a), the threshold voltage is 0.0 V in the initial HCS evaluation (25 °C) and 3.5 V after the HCS evaluation at 60 °C for 1000 s. Moreover, the threshold voltage continuously shifts in the positive direction with a total change (ΔVth) of 3.5 V. The sub-threshold swing (SS) value is slightly increased from 0.09 to 0.16 V/dec. For the BCE-structured TFT, the threshold voltage is much higher, namely, 4.0 V at 25 °C, and increases to 11.2 V after HCS evaluation at 60 °C for 1000 s. A possible reason for these high threshold voltages is the diffusion of Cu+ into the a-IGZO film during the wet etching process of the BCE process. Cu+ can act as accepter-type defect sites in a-IGZO films, and a high density of Cu+ can trap a large number of electrons. The trapped electrons generate a screened coulombic potential that results in the transient threshold voltage shift phenomenon. Generally, the gate insulator bulk and the newly formed defect sites inside the bulk of the a-IGZO films can increase the SS value of TFTs . These results clearly explain the decrease of the Ids residual current in the BCE-structured TFTs. However, the SS value of the BCE-structured TFT shows a tendency to decrease from 0.46 to 0.24 V/dec. This decreasing SS value results from electrons accumulating near the a-IGZO interface, after which the gate insulator can rapidly fill up the high levels of the accepter-type trap sites that existed initially. Moreover, the trap sites are filled faster than they are generated by the HCS, and therefore, the number of trapped electrons gradually decreases over time. This agrees with the positively shifting behavior of the threshold voltage.
As for the uniformity of the characteristics for CL-ES, because ESL provides active back channel protection from Cu+ contamination and etchant damage, its result is stable compared to that of BCE. In addition, it should be noted that the characteristics of the output curve show no differences for BCE and can promise CL-ES production and stability (Table 2, Fig. 7e, f).
Figure 7 c and d show the results of the sub-threshold swing and threshold voltage behavior along with the HCS evaluation progress. Generally, the sub-threshold swing value of the GOA TFT gradually increases, as seen for the CL-ES-structured TFT (Fig. 7d). However, the BCE-structured TFT shows abnormal behavior, with the sub-threshold swing value increasing initially and subsequently decreasing during the HCS evaluation. The SS value of the BCE-structured TFT increases from 0.46 to 0.55 V/dec when the substrate temperature increased from 25 to 60 °C. At the same time, the threshold voltage negatively shifts from 4.0 to 2.9 V (Fig. 7c). This abnormal phenomenon results from the damage of the a-IGZO film surface by the H2O2 etchant with added fluoride. As mentioned before, the surface damage of the a-IGZO films implies a lack of Zn, Ga, and oxygen atoms, which forms numerous defect sites, including oxygen vacancies. It is believed that these defect sites are active as shallow-donor-like states, which are close to the minimum conduction band, and are capable of thermal excitation and acting as electron sources for the conduction band, leading to a degradation of the a-IGZO TFT characteristics. Based on the above results, the CL-ES-structured TFT with small-accepter-like states and oxygen deficiencies that act as shallow-donor-like states is a much better structure than the BCE-structured TFT.
In conclusion, we demonstrate that CL-ES-structured GOA TFT, with a decreased device feature size and a clean etch stopper layer, can significantly improve the device performance and stability. With the proposed CL-ES-structured TFT manufacturing process, the damage and contamination of the TFT back channel are minimized. In addition, for the same degree of integration as that of the BCE-structured GOA TFT, the CL-ES-structured TFT process can meet the goals of aesthetic design and manufacturing cost efficiency. The CL-ES-structured GOA TFT shows excellent electrical performance compared to that of the BCE-structured GOA TFT, including a much higher residual ion current (~ 187%), much lower initial SS value (0.09 V/dec), and a much lower variation of the threshold voltage (3.5 V). This implies the possibility of GOA designs with much higher integration and reliability. The enhanced performance and stability suggest that the CL-ES-structured TFT, with a simplified process and a clean etch stopper layer, successfully overcomes the donor-like defects caused by oxygen deficiencies and the accepter-like defects caused by Cu+ diffusion during the BCE process. Therefore, a clean surface composition for the a-IGZO channel region in CL-ES-structured TFTs is important for the production of a-IGZO TFT backplanes with high-reliability, high-resolution, and narrow-bezel displays.
Gate drive IC on array
Liquid crystal display
Plasma-enhanced chemical vapor deposition
Etch stopper layer
Back channel etch
High current stress
Sugawara M, Masaoka K (2013) UHDTV image format for better visual experience. Proc IEEE 101:8–17
Petti L, Münzenrieder N, Vogt C, Faber H, Büthe L, Cantarella G, Bottacchi F, Anthopoulos TD, Tröster G (2016) Metal oxide semiconductor thin-film transistors for flexible electronics. Appl Phys Rev 3:021303
Xu WY, Li H, Xu JB, Wang L (2018) Recent advances of solution-processed metal oxide thin-film transistors. ACS Appl Mater Interfaces 10:25878–25901
Geng D, Chen YF, Mativenga M, Jang J (2015) 30 μm-pitch oxide TFT-based gate driver design for small-size, high-resolution, and narrow-bezel display. IEEE Electron Device Lett 36:805–807
Liao CW, Hu ZJ, Li JM, Li WJ, Cao SJ, Zhang SD (2015) A simple low temperature workable a-Si:H TFT integrated gate driver on array. SID 46:1316–1319
Yamada S, Shimoshikiryoh F, Itoh Y, Ban A (2016) 37-4 L: Late-news paper: development of a 27-in. 8 K x 4 K Liquid-Crystal Display Utilizing an InGaZnO TFT Backplane. Dig Tech Pap Soc Inf Disp Int Symp. 47:480–483
Ge SM, Li S, Chen SJ, Kong XY, Meng YH, Shi W, Zhao Y (2017) 42-1: Development of Cu BCE-structure IGZO TFT for a high-ppi 31-in. 8 K× 4 K GOA LCD. Dig Tech Pap Soc Inf Disp Int Symp. 48:592–595
Park SJ, Kim CH, Lee WJ, Sung S, Yoon MH (2014) Sol-gel metal oxide dielectrics for all-solution-processed electronics. 114:1–22
Kim M, Jeong JH, Lee HJ, Ahn TK, Shin HS, Park JS, Kim HD (2007) High mobility bottom gate InGaZnO thin film transistors with SiOx etch stopper. Appl Phys Lett 90:212114–212116
Um JG, Mativenga M, Geng D, Li X, Jang J (2014) P-7: High speed a-IGZO TFT-based gate driver by using back channel etched structure. Dig Tech Pap Soc Inf Disp Int Symp. 45:968–971
Kenji N, Toshio K, Hideo H (2011) Highly stable amorphous In-Ga-Zn-O thin-film transistors produced by eliminating deep subgap defects. Appl Phys Lett 99:488
Takechi K, Nakata M, Kanoh H, Otsuki S, Kaneko S (2006) Dependence of self-heating effects on operation conditions and device structures for polycrystalline silicon TFTs. IEEE Trans Electron Devices 53:251–257
Hsieh TY, Chang TC, Chen TC, Chen YT, Tsai MY, Chu AK, Chen CY (2013) Self-heating-effect-induced degradation behaviors in a-InGaZnO thin-film transistors. IEEE Electron Device Lett 34:63–65
Mallory M, Sejin H, Jin J (2013) High current stress effects in amorphous-InGaZnO4 thin-film transistors. Appl Phys Lett 102:488
Sang HR, Park YC, Mativenga M, Dong HK, Jin J (2014) Amorphous-InGaZnO4 thin-film transistors with damage-free back channel wet-etch process. ECS Solid State Lett. 1:17–19
Li X, Geng D, Mativenga M, Jang J (2014) High-speed dual-gate a-IGZO TFT-based circuits with top-gate offset structure. IEEE Electron Device Lett. 35:461–463
Ochi M, Morita S, Takanashi Y (2015) Electrical characterization of BCE-TFTs with a-IGZTO oxide semiconductor compatible with Cu and Al interconnections. SID 2015 DIGEST 57:853–856
Chung JM, Zhang XK, Shang F, Kim JH, Wang XL, Liu S, Yang BG, Xiang Y (2018) Enhancement of a-IGZO TFT device performance using a clean interface process via etch-stopper nano-layers. Nanoscale Res Lett 13:164–172
Kamiya T, Nomura K, Hosono H (2009) Origins of high mobility and low operation voltage of amorphous oxide TFTs: electronic structure, electron transport, defects and doping. J Disp Technol. 5:468–483
Kwon JY, Jeong JK (2015) Recent progress in high performance and reliable n-type transition metal oxide-based thin film transistors. Semicond Sci Technol. 30:024002–024017
Yao J, Xu N, Deng S, Chen J, She J, Shieh HPD, Huang YP (2011) Electrical and photosensitive characteristics of a-IGZO TFTs related to oxygen vacancy. IEEE Trans Electron Devices 58:1121–1126
This work is supported by the Chongqing BOE Optoelectronics (CQ1610-PM-IP-001) and National Natural Science Foundation of China (G0501200151472044).
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Chung, J., Wu, F., Jeong, S. et al. Enhanced Reliability of a-IGZO TFTs with a Reduced Feature Size and a Clean Etch-Stopper Layer Structure. Nanoscale Res Lett 14, 165 (2019) doi:10.1186/s11671-019-3001-3
- Gate drive IC on array (GOA)
- Thin-film transistors (TFTs)
- Back channel etch
- Etch stopper layer