- Nano Express
- Open Access
Novel High Holding Voltage SCR with Embedded Carrier Recombination Structure for Latch-up Immune and Robust ESD Protection
© The Author(s). 2019
- Received: 24 January 2019
- Accepted: 15 May 2019
- Published: 28 May 2019
A novel CMOS-process-compatible high-holding voltage silicon-controlled rectifier (HHV-SCR) for electrostatic discharge (ESD) protection is proposed and demonstrated by simulation and transmission line pulse (TLP) testing. The newly introduced hole (or electron) recombination region H-RR (or E-RR) not only recombines the minority carrier in parasitic PNP (or NPN) transistor base by N+ (or P+) layer, but provides the additional recombination to eliminate the surface avalanche carriers by newly added P+ (or N+) layer in H-RR (or E-RR), which brings about a further improvement of holding voltage (Vh). Compared with the measured Vh of 1.8 V of low-voltage triggered silicon-controlled rectifier (LVTSCR), the Vh of HHV-SCR can be increased to 8.1 V while maintaining a sufficiently high failure current (It2 > 2.6 A). An improvement of over four times in the figure of merit (FOM) is achieved.
- Electrostatic discharge (ESD)
- Silicon-controlled rectifier (SCR)
- Holding voltage (V h)
- Transmission line pulse (TLP)
With the development of semiconductor integrated technology and the consistent miniaturization of semiconductor device’s feature size, the device damage induced by ESD is becoming more severe. At the cost of large chip area, the conventional devices such as diode and gate grounded N-channel MOSFET (ggNMOS) featuring normal ESD robustness were reported . In order to realize improved ESD capability with a smaller device dimension, the low-voltage triggered silicon-controlled rectifier (LVTSCR) has been considered as an attractive device due to its high-current capability per unit area . For low-voltage applications, owing to the embedded low-trigger voltage (Vt1) ggNMOS, the LVTSCR with excellent ESD robustness is capable of providing faster ESD response speed than that obtained in conventional SCR. However, the strong inherent positive feedback causes an extremely low Vh (1~2 V), which is responsible for latch-up and transient mis-trigger . Such negative effects can be effectively suppressed by simply increasing Vh [3–11]. The device will be free from the latch-up and transient mis-trigger, while the Vh is higher than the power supply voltage (VDD). Accordingly, The N+ESD region and P+LDD region were added into SCR with additional masks and ion implant steps to improve Vh . However, the ESD robustness may deteriorate due to the additional power dissipation together with the increased Vh. In addition, the emitter voltage clamp technology for Vh improvement with acceptable failure current (It2) was also proposed . Nevertheless, the Vh in the aforementioned approaches is non-adjustable which still presents inconvenience and limitation in versatile applications.
In this letter, a novel high-holding voltage silicon-controlled rectifier (HHV-SCR) is proposed and demonstrated by TCAD simulation and TLP testing. The device simultaneously achieves high Vh, high It2, and adjustable Vh without any additional masks and steps. The TLP-test was carried out to validate that the Vh can be effectively improved while maintaining a sufficiently high It2. According to the tested results, the HHV-SCR features over four times higher Vh than that in the LVTSCR with the negligible degradation in It2.
In this work, a novel high-holding voltage SCR with an embedded carrier recombination structure is investigated. The physical models IMPACT.I, BGN, CONMOB, FLDMOB, SRH, and SRFMOB are used in numerical simulation. Based on the model, H-RR and E-RR are optimized to achieve high Vh and high PM. The fabricated HHV-SCRs and LVTSCR are tested by TLP system.
Comparison of experimental results
V CL @1.3 A
V CL @1.3 A
List of Abbreviations
High-holding voltage silicon-controlled rectifier
Transmission line pulse
Hole recombination regions
Electron recombination regions
Gate grounded N-channel MOSFET
Low-voltage triggered SCR
A novel CMOS-process-compatibleHHV-SCR is studied and measured by TCAD simulation and TLP system. Compared with the conventional LVTSCR, the HHV-SCR features significantly improved Vh (an improvement of over 450% in the Vh is achieved) and without sacrificing the chip area. Furthermore, the Vh of the HHV-SCR can be adjusted from 5.5 V to 8.1 V to satisfy the different Vh requirements with negligible degradation in It2. In terms of PM, compared with the conventional LVTSCR, over 200% improvement is also achieved.
This work was supported in part by the National Natural Science Foundation of China under contract 61674027, in part by the China Postdoctoral Science Foundation Funded Project under Grant 2017M612942, and in part by the Natural Science Foundation of Guangdong Province under grant 2016A030311022 and 2018A030310015, in part by the Applied Fundamental Research Project of Sichuan Province under grant 18YYJC0482, and in part by the Fundamental Research Funds for the Central Universities under grant ZYGX2016J210.
ZW proposed the novel structure and was a major contributor in writing the manuscript. ZQ was a major contributor in simulating the devices. LL drew the layouts and tested the devices. MQ verified the results and revised the manuscript. Others authors offered comments and revised the manuscript. All authors read and approved the final manuscript.
The authors declare that they have no competing interests.
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