Fig. 1

VLSI-Fi: Conceptual schematics of the VLSI-Fi technique representing the “2D + 1D + 0D” approach. a The 3D-printed preform a (I) is thermally drawn a (II) into a long, thin fiber that preserves the cross-sectional geometry of the preform (2D). b Axial patterning of the fiber via spatially coherent, material-selective capillary breakup (+1D), resulting in the assembly of initially continuous, separate cores into arrays of discrete devices contacted in parallel. c Segregation-driven control of doping in post-breakup semiconducting particles, allowing control of an individual device’s internal architecture c (II) via thermal gradient c (III). d (I) Schematic illustration of Metal-oxide-semiconductor field-effect transistor (MOSFET) through VLSI-Fi, where the p-type and n-type semiconductors are shown in blue and red, respectively. The golden continuous rods embedded in a silica fiber act as gate, source, and drain. The resulting fiber cross section is shown in d (II). Similarly, e (I) shows a schematic picture of a bipolar junction transistor (BJT) realized by VLSI-Fi, achieved with impinging heat sources from both the emitter and collector sides. The fiber cross section e (II) shows the emitter, collector, and base of the BJT (continuous rods embedded in the fiber), with the p-type and n-type semiconductors of the n-p-n junction shown in blue and red, respectively