Skip to main content

High Mobility Ge pMOSFETs with ZrO2 Dielectric: Impacts of Post Annealing


This paper investigates the impacts of post metal annealing (PMA) and post deposition annealing (PDA) on the electrical performance of Ge p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ZrO2 dielectric. For the transistors without PDA, on-state current (ION), subthreshold swing (SS), and capacitance equivalent thickness (CET) characteristics are improved with PMA temperature increasing from 350 to 500 °C. Crystallization of ZrO2 dielectric at the higher PMA temperature contributes to the increase of the permittivity of ZrO2 and the decrease of the density of interface states (Dit), resulting in a reduced CET and high effective hole mobility (μeff). It is demonstrated that Ge pMOSFETs with a PDA treatment at 400 °C have a lower CET and a steeper SS but a lower μeff compared to devices without PDA.


Germanium (Ge) has been regarded as one of the attractive p-channel materials for advanced CMOS because it offers much higher hole mobility than does Si [1,2,3]. A high-quality gate dielectric and effective passivation of Ge surface are the keys to realizing the superior effective carrier mobility (μeff) and high drive current in Ge transistor [4,5,6,7]. Several high-κ materials such as HfO2 [8], ZrO2 [7, 9], La2O3 [10], and Y2O3 [11] have been studied as the alternative gate dielectrics for Ge p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) to achieve capacitance equivalent thickness (CET) scalability toward sub-1 nm. Among these, ZrO2 dielectric has attracted most attention due to the much higher κ value [12, 13] and the better interfacial quality [14] compared to the Hf-based ones. It has widely been reported that crystallization of ZrO2 can further improve the electrical performance of Ge pMOSFET, e.g., reducing CET and boosting μeff [15, 16]. However, there is a lack of study on the impacts of process steps for ZrO2 crystallization on device performance of Ge transistors.

In this paper, we investigate the impacts of the post metal annealing (PMA) and the post deposition annealing (PDA) on the electrical performance of Ge pMOSFETs with ZrO2 dielectric. Significantly improved μeff and reduced CET can be achieved in devices at higher PMA temperature.


Key process steps for fabricating Ge pMOSFETs with ZrO2 dielectric are shown in Fig. 1a. The Ge pMOSFETs were fabricated on n-type Ge(001) wafer with a resistivity of 0.088–0.14 Ω∙cm. After the several cycles of chemical cleaning in the diluted HF (1:50) solution and rinsing in DI water. Ge wafer was loaded into an atomic layer deposition (ALD) chamber. The Ge surface was passivated by an ozone post oxidation (OPO), i.e., an ultrathin Al2O3 layer was deposited at 300 °C, and then, the in situ OPO was carried out at 300 °C for 15 min. After that, a 5-nm-thick ZrO2 was deposited at 250 °C in the same ALD chamber using TDMAZr and H2O as precursors of Zr and O, respectively. During the deposition, Zr[N(CH3)2]4 source was heated to 85 °C. PDA process was carried out on some sample at 400 °C for 60 s using the rapid thermal annealing. Samples with and without PDA were denoted wafer II and I, respectively. Then, a 100-nm-thick TaN gate electrode was deposited by reactive sputtering. After the gate patterning and etching, the source/drain (S/D) regions were formed by BF2+ implantation at an energy of 30 keV and a dose of 1 × 1015 cm−2. Fifteen-nanometer nickel S/D contacts were formed by a lift-off process. Finally, the PMA at 350, 400, 450, and 500 °C for 30 s was carried out for dopant activation and S/D metallization.

Fig. 1
figure 1

a Key process steps for fabricating Ge pMOSFETs with ZrO2 dielectric. b SEM image of the fabricated transistor. c XTEM image of Ge pMOSFET showing the gate and S/D regions. d, e HRTEM images of gate stacks of Ge pMOSFETs on wafer I annealed at 400 °C and 500 °C, respectively

Figure 1b shows the scanning electron microscope (SEM) image of a fabricated Ge pMOSFET. Figure 1c shows the cross-sectional transmission electron microscope (XTEM) image of Ge pMOSFET, showing the source/drain region, metal gate, and ZrO2 dielectric. Figure 1d and e show the high-resolution TEM (HRTEM) images of the gate stacks of Ge pMOSFETs with a PMA at 400 and 500 °C, respectively, on wafer I. It is observed that the ZrO2 dielectric was fully crystallized and underwent a PMA at 500 °C. The thickness of Al2O3 interfacial layer is about 0.7 nm.

Results and Discussion

Inversion capacitance Cinv vs. VGS curves measured at a frequency of 300 kHz for the devices on wafer I are shown in Fig. 2. The CET values are extracted to be  1.95, 1.80, 1.67, and 1.52 nm for the devices with PMA at 350, 400, 450, and 500 °C, respectively. The smaller CET is achieved at a higher PMA temperature due to the crystallization of ZrO2. In general, the κ values for amorphous and crystalline ZrO2 are about 20–23 and 28–30, respectively. A 5-nm-thick crystalline ZrO2 contributes an EOT of ~ 0.7 nm. The shift of C-V curves with various PMA temperature is due to the fact that crystallization reduces the density of bulk traps in ZrO2 dielectric.

Fig. 2
figure 2

Inversion Cinv-VGS curves for the Ge pMOSFETs on wafer I with a PMA at 350 °C, 400 °C, 450 °C, and 500 °C

Figure 3a shows the measured transfer characteristics and gate leakage currents IG of Ge pMOSFETs on wafer I with the different PMA temperatures. All the devices have a gate length LG of 4 μm and a gate width W of 100 μm. Ge pMOSFETs exhibit the much lower IG compared to IDS for all the PMA temperatures. An ION/IOFF ratio above 104 is achieved for the device with a PMA at 500 °C. The IDS-VDS curves of the devices measured at the different gate overdrive |VGS-VTH| are shown in Fig. 3b. It is noted that the threshold voltage VTH is defined as the VGS at IDS of 10−7 A/μm. The Ge transistor with a PMA at 500 °C obtains the ~ 47% and 118% drive current improvement compared to the devices annealed at 450 °C and 350 °C, respectively, at a VDS of − 1.0 V and a |VGS-VTH| of 0.8 V. Figure 3c shows the statistical plot of the ION at a VDS of − 0.5 V and a VGS-VTH of − 1 V for Ge pMOSFETs with the various PMA temperatures. All the transistors in this plot have an LG of 4 μm and a W of 100 μm. Devices with a PMA at 500 °C exhibit an improved ION as compared to those with the lower PMA temperatures, which is attributed to the decreased S/D resistance, the reduced CET, and the higher μeff, which will be discussed later.

Fig. 3
figure 3

a Measured ID, IS, and IG vs. VGS curves of Ge pMOSFETs on wafer I with the PMA at 350, 400, 450, and 500 °C. b IDS-VDS curves measured at the different VGS-VTH for the devices. c Device annealed at 500 °C has a higher on-state current ION compared to the transistors with the PMA at the lower temperatures

Figure 4 shows the statistical plots of midgap Dit, SS, and VTH characteristics for the devices with the different PMA temperatures. As shown in Fig. 4a, based on the maximum conductance method [17], the midgap Dit values are extracted to be 1.3 × 1013, 9.5 × 1012, 9.2 × 1012, and 6.3 × 1012 cm−2 eV−1 for the devices with the PMA at 350, 400, 450, and 500 °C, respectively. Figure 4b presents that Ge pMOSFETs annealed at 500 °C have the improved SS characteristics than the transistors annealed at the lower temperatures, due to the smaller midgap Dit and CET. The values of Dit and SS of Ge pMOSFETs with PMA are still higher than those of the best reported Ge transistors. It could possibly be reduced by optimizing the OPO passivation module, e.g., Al2O3 thickness and ozone oxidation temperature and duration. VTH shifts to the positive VGS with the increasing of PMA temperature, which is originated from the reduced CET and Dit. It is concluded that the best electrical performance is achieved for Ge pMOSFETs with a PMA at 500 °C.

Fig. 4
figure 4

Comparison of a midgap Dit, b SS, and c VTH for Ge pMOSFETs on wafer I with the PMA at 350, 400, 450, and 500 °C

μeff, as a crucial factor affecting device drive current and transconductance in Ge pMOSFETs, was measured using the ΔRtotLG method [18]. A large number of devices were measured with LG ranging from 1.5 to 9 μm. Figure 5a illustrates the total resistance Rtot extracted at a |VGS-VTH| of − 1 V and a VDS of − 0.05 V as a function of LG. The RSD is the value at which the fitted line intersects at the y-axis. The RSD values were estimated about to be 7.85, 7.15, 6.10, and 4.35  kΩ ·μm for devices with PMA at 350, 400, 450, and 500 °C, respectively. This is indicative of the better dopant activation of S/D at higher PMA temperature. μeff can be extracted by μeff = 1/[WQinvRtotLG)], where Qinv is the inversion charge density in Ge channel and ΔRtotLG is the slope of the Rtot vs. LG as shown in Fig. 5a. The smaller ΔRtotLG for devices with PMA at 500 °C indicates an enhancement in μeff as compared with transistors with PMA at 450 °C. Figure 5b shows μeff as a function of Qinv curves, extracted using the split C-V method. The peak hole mobility is 384 cm2/V ·s for devices with a PMA at 500 °C, which is 31% higher than that of the devices with a PMA at 400 °C. At a high Qinv of 1 × 1013 cm−2, Ge pMOSFETs which underwent a PMA at 500 °C achieve a mobility enhancement in comparison with the devices annealed at 400 °C. Ge transistors with crystalline ZrO2 have the lower density of bulk trap charge resulting in the lower remote Coulomb scattering of holes, compared to the devices with amorphous ZrO2. Owing to the smooth interface between crystalline ZrO2 and Ge, Ge devices annealed at 500 °C have a lower surface roughness scattering and show a shift of peak mobility to the higher Qinv.

Fig. 5
figure 5

a Rtot as a function of LG at a VGS-VTH of − 1 V and a VDS of − 0.05 V for devices on wafer I with various PMA temperatures. b μeff vs. Qinv extracted by the split C-V method. The highest mobility is obtained in devices with a PMA at 500 °C

Next, we discuss the impacts of PDA on the electrical characteristics of Ge pMOSFETs. Figure 6 shows the measured Cinv vs. VGS of the Ge pMOSFETs on wafer I and wafer II with a PMA at 400 °C. The device which underwent a PDA at 400 °C has a much lower CET value of 1.29 nm compared to the device without PDA, 1.80 nm. Figure 7a shows the ID, IS, and IG-VGS characteristic curves of Ge pMOSFETs on wafer I and wafer II, and the devices which underwent a PMA at 400 °C. A larger gate leakage current is obtained for the device with PDA compared to the transistor without PDA, which is due to the lower CET. The corresponding IDS-VDS curves of the devices measured at different gate overdrive VGS-VTH are shown in Fig. 7b. The Ge transistor without PDA shows a ~ 24% improvement in drive current over the one with PDA at 400 °C at the same overdrive of − 0.8 V in the saturation region.

Fig. 6
figure 6

Cinv-VGS plots for the devices on wafer I and II with a PMA at 400 °C

Fig. 7
figure 7

a ID, IS, and IG vs. VGS curves of Ge pMOSFETs on wafer I and II with PMA at 400 °C. b IDS-VDS curves measured at different VGS-VTH for the devices

Figure 8 plots the statistical results of midgap Dit, SS, and VTH of the Ge pMOSFETs with and without PDA. Figure 8a shows that the smaller Dit is achieved in Ge pMOSFETs with PDA at 400 °C compared to devices without PDA. In Fig. 8b, the lower value of mean subthreshold swing of 142 mV/decade is achieved for devices with PDA at 400 °C, corresponding to the lower CET and the lower Dit. It indicates that devices with PDA at 400 °C have a superior ZrO2/Ge interface. Figure 8c shows that devices with and without PDA have a different VTH; it may be attributed to the density of traps in the lower bandgap half dominant in the VTH.

Fig. 8
figure 8

Comparison of a midgap Dit, b SS, and c VTH for Ge pMOSFETs on wafer I and II with PMA at 400 °C

Figure 9a shows the Rtot vs. LG curves at a gate overdrive of − 1 V and VDS of − 0.05 V for devices with a PMA at 400 °C. The RSD values are estimated about to be 7.15 and 7.30 kΩ·μm for devices without and with PDA at 400 °C, respectively. As shown in Fig. 9b, a remarkable higher peak μeff is achieved for Ge pMOSFETs without PDA, corresponding the smaller ΔRtotLG in Fig. 9a, compared to devices with PDA. The devices with a PDA at 400 °C exhibit a peak μeff of 211 cm2/V·s; the lower hole mobility might be mainly attributed to the strong remote Coulomb scattering contributed by the fixed charge in ZrO2 dielectric.

Fig. 9
figure 9

a Rtot vs. LG curves for devices on wafer I and wafer II with PMA at 400 °C. b Hole mobility μeff vs. Qinv for devices with and without PDA


In summary, the impacts of PMA and PDA on Ge pMOSFET with ZrO2 dielectric were extensively investigated. Crystallization of ZrO2 gate dielectric provides for significantly enhanced hole mobility and reduced CET compared to devices at the lower PMA temperature. A peak hole mobility of 384 cm2/V·s and enhanced drive current have been achieved in devices with PMA at 500 °C. Devices with PDA at 400 °C exhibited the lower CET and the smaller Dit but the poor hole mobility and the larger leakage current compared with transistors without PDA.

Availability of Data and Materials

The datasets supporting the conclusions of this article are included in the article.



Atomic layer deposition

BF2 + :

Boron fluoride ion


Capacitive effective thickness




Hydrofluoric acid


High-resolution transmission electron microscope


Interfacial layer


Metal-oxide-semiconductor field-effect transistors




Post deposition annealing


Post metal annealing


Subthreshold swing


Tantalum nitride


Tetrakis (dimethylamido) hafnium

ZrO2 :

Zirconium dioxide

μ eff :

Effective carrier mobility


  1. Duriez B, Vellianitis G, van Dal MJH, Doornbos G, Oxland R, Bhuwalka KK, Holland M, Chang YS, Hsieh CH, Yin KM, See YC, Passlack M, Diaz CH (2013) Scaled p-channel Ge FinFET with optimized gate stack and record performance integrated on 300 mm Si wafers. IEDM Tech Dig, pp 522–525

  2. Chern W, Hashemi P, Teherani JT, Yu T, Dong Y, Xia G, Antoniadis DA, Hoyt JL (2012) High mobility high-κ-all-around asymmetrically-strained germanium nanowire trigate p-MOSFETs. In: IEDM Tech Dig, pp 387–390

    Google Scholar 

  3. Wu H, Luo W, Si M, Zhang J, Zhou H, Ye PD (2014) Deep sub-100 nm Ge CMOS devices on Si with the recessed S/D and channel. In: IEDM Tech Dig, pp 16.7.1–16.7.4

    Google Scholar 

  4. Lee CH, Nishimura T, Tabata T, Wang SK, Nagashio K, Kita K, Toriumi A (2010) Ge MOSFETs performance: impact of Ge interface passivation. In: IEDM Tech Dig, pp 18.1.1–18.1.4

    Google Scholar 

  5. Pillarisetty R, Chu-Kung B, Corcoran S, Dewey G, Kavalieros J, Kennel H, Kotlyar R, Le V, Lionberger D, Metz M, Mukherjee N, Nah J, Rachmady W, Radosavljevic M, Shah U, Taft S, Then H, Zelick N, Chau R (2010) High mobility strained germanium quantum well field effect transistor as the p-channel device option for low power (Vcc = 0.5 V) III-V CMOS architecture. In: IEDM Tech Dig, pp 150–153

    Google Scholar 

  6. Hashemi P, Chern W, Lee H, Teherani JT, Zhu Y, Gonsalvez J, Shahidi GG, Hoyt JL (2012) Ultrathin strained-Ge channel p-MOSFETs with high-k/metal gate and sub-1-nm equivalent oxide thickness. IEEE Electron Device Lett 33:943–945

    Article  CAS  Google Scholar 

  7. Shin Y, Chung W, Seo Y, Lee CH, Sohn DK, Cho BJ (2014) Demonstration of Ge pMOSFETs with 6 Å EOT using TaN/ZrO2/Zr-cap/n-Ge(100) gate stack fabricated by novel vacuum annealing and in-situ metal capping method. In: VLSI Tech Dig, pp 82–83

    Google Scholar 

  8. Yi SH, Chang-Liao KS, Wu TY, Hsu CW, Huang J (2017) High performance Ge pMOSFETs with HfO2/Hf-Cap/GeOx gate stack and suitable post metal annealing treatments. IEEE Trans Electron Devices 37:544–547

    Article  Google Scholar 

  9. Lin CM, Chang HC, Chen YT, Wong IH, Lan HS, Luo SJ, Lin JY, Tseng YJ, Liu CW, Hu C, Yang FL (2012) Interfacial layer-free ZrO2 on Ge with 0.39-nm EOT, κ~43, ~2 × 10-3 A/cm2 gate leakage, SS =85 mV/dec, Ion/Ioff = 6 × 105, and high strain response. In: IEDM Tech Dig, pp 23.2.1–23.2.4

    Google Scholar 

  10. Henkel C, Abermann S, Bethge O, Pozzovivo G, Klang P, Reiche M, Bertagnolli E (2010) Ge p-MOSFETs with scaled ALD La2O3/ZrO2 gate dielectrics. IEEE Trans Electron Devices 57:3295–3302

    Article  CAS  Google Scholar 

  11. Seo Y, Lee TI, Yoon CM, Park BE, Hwang WS, Kim H (2017) The impact of an ultrathin Y2O3 layer on GeO2 passivation in Ge MOS gate stacks. IEEE Trans Electron Devices 64:3303–3307

    Article  CAS  Google Scholar 

  12. Chui CO, Ramanathan S, Triplett BB, Mcintyre PC, Saraswat KC (2002) Germanium MOS capacitors incorporating ultrathin high-κ gate dielectric. IEEE Electron Device Lett 23:473–475

    Article  CAS  Google Scholar 

  13. Kamata Y, Kamimuta Y, Ino T, Iijima R, Koyama M, Nishiyama A (2005) Influences of activation annealing on characteristics of Ge p-MOSFET with ZrO2 gate dielectric. In: Proc. Ext. Abst. SSDM, pp 856–857

    Google Scholar 

  14. Kamata Y, Kamimuta Y, Ino T, Nishiyama A (2005) Direct comparison of ZrO2 and HfO2 on ge substrate in terms of the realization of ultrathin high-κ gate stacks. Jpn J Appl Phys 44:2323–2329

    Article  CAS  Google Scholar 

  15. Li CC, Chang-Liao KS, Chi WF, Li MC, Chen TC, Su TH, Chang YW, Tsai CC, Liu LJ, Fu CH, Lu CC (2016) Improved electrical characteristics of Ge pMOSFETs with ZrO2/HfO2 stack gate dielectric. IEEE Electron Device Lett 37:12–15

    Article  CAS  Google Scholar 

  16. Liu H, Han GQ, Xu Y, Liu Y, Liu TJK, Hao Y (2019) High-mobility Ge pMOSFETs with crystalline ZrO2 dielectric. IEEE Electron Device Lett 40:371–374

    Article  Google Scholar 

  17. Hill WA, Coleman CC (1980) A single-frequency approximation for interface-state density determination. Solid State Electronics 23:987–993

    Article  CAS  Google Scholar 

  18. Greve DW (1998) Field effect devices and application: devices for portable, low-power, and imaging systems. Prentice-Hall, Englewood

    Google Scholar 

Download references


Not applicable.


The authors acknowledge the support from the National Natural Science Foundation of China under Grant No. 61534004, 61604112, 61622405, 61874081, and 61851406

Author information

Authors and Affiliations



HL carried out the experiments and drafted the manuscript. GQH and YL supported the study and helped to revise the manuscript. YH provided constructive advice in the drafting. All the authors read and approved the final manuscript.

Corresponding author

Correspondence to Genquan Han.

Ethics declarations

Competing Interests

The authors declare that they have no competing interests.

Additional information

Publisher’s Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Open Access This article is distributed under the terms of the Creative Commons Attribution 4.0 International License (, which permits unrestricted use, distribution, and reproduction in any medium, provided you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license, and indicate if changes were made.

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Liu, H., Han, G., Liu, Y. et al. High Mobility Ge pMOSFETs with ZrO2 Dielectric: Impacts of Post Annealing. Nanoscale Res Lett 14, 202 (2019).

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI:


  • Germanium
  • ZrO2
  • PMA
  • PDA
  • Mobility