Fig. 1From: Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping LayerThe cross section schematic diagrams of the a-IGZO TFT memory device programmed under a positive gate bias (a) and a negative gate bias (b), respectively.Back to article page