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Fig. 2 | Nanoscale Research Letters

Fig. 2

From: Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

Fig. 2

The transfer curves of the a-IGZO TFT memory device and those programmed a at various positive gate biases for a constant time of 80 ms, b at various negative gate biases for a constant time of 80 ms, c at 13 V for various programming time, and d at −13 V for various programming time. All the transfer curves for each figure were measured on the same device, and all programming operations were carried out in sequence.

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