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Table 1 Comparisons of the programming and erasing characteristics of various a-IGZO TFT memories with different gate stacks

From: Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer

Gate stack

Programming conditions

ΔVth-P

Erasing conditions

ΔVth-E

Ref.

Al2O3/Al2O3/Al2O3

Vg = 10 V/10 ms

2 V

−10 V/100 s

−0.2 V

[14]

SiO2/SmTiO3/SiO2

Vg = 15 V/100ms

2.7 V

−15 V/100 ms

−2.2 V

[22]

SiO2/ErTixOy/SiO2

Vg = 20V/100 ms

3.9 V

−20 V/100 ms

−3.9 V

[23]

Al2O3/ZnO/Al2O3

Vg = 13 V/1 μs

2 V

−12 V/10 μs

−7.2 V

This work

  1. ΔVth-P means the threshold voltage shift relative to the pristine device after programming and ΔVth-E implies the threshold voltage shift relative to the programmed device after erasing

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