Fig. 5From: Test Pattern Design for Plasma Induced Damage on Inter-Metal Dielectric in FinFET Cu BEOL ProcessesSchematics and the wafer maps showing the distributions of (a) the PID voltage and VBD from (b) test pattern I and (c) II, showing the regional effect within the circled area from plasma-induced damage on the back-end dielectric layer that can be attributed to the regional plasma charging levelsBack to article page