 Nano Express
 Open Access
 Published:
A 180 nm Selfbiased Bandgap Reference with High PSRR Enhancement
Nanoscale Research Letters volume 15, Article number: 104 (2020)
Abstract
In this paper, an improved selfbiased bandgap reference (BGR) with high power supply rejection ratio (PSRR) is presented. An operational amplifier constructing feedback loop is multiplexed with the generation of positive temperature coefficient (TC) voltage for lower power consumption, where an offset voltage is adopted to achieve proportional to absolute temperature (PTAT) voltage. With the temperatureindependent reference generation, two feedback loops are realized at the same time for PSRR enhancement, which form a local negative feedback loop (LNFL) and a global selfbiased loop (GSBL). The proposed BGR is implemented in a 180 nm BCD technology, whose results show that the generated reference voltage is 2.506 V, and the TC is 25 ppm/°C in the temperature range of −55 to 125 °C. The line sensitivity (LS) is 0.08 ‰/V. Without any filter capacitor, the PSRR is 76 dB at low frequencies, over 46 dB up to 1 MHz.
Introduction
Voltage reference is one of the core modules in electronic systems, which is widely used in medical electronics, power managements, wireless environmental sensors, and communication circuits. With the improvement of technology, the area of chip continues to shrink, and the antiinterference ability continues to increase, and the requirements for structural optimization and noise immunity of voltage reference are increasing dramatically, especially in nanoscale applications [1].
Conventional bandgap reference (BGR) circuits require additional circuit blocks to provide bias current for the entire circuit, which greatly increases the circuit area and power consumption. At the same time, the generated bias current is greatly affected by temperature, which affects the temperature coefficient (TC) of the reference voltage. Lots of highorder compensated techniques for improved TC have been reported, such as piecewise curvature compensation [2], exponential curvature compensation [3], leakagebased square root compensation (LSRC) [4], and so on. Another disadvantage of the conventional BGR circuit is that it is greatly affected by the external environment and the output voltage is unstable, which is the focus of this article.
Power supply rejection ratio (PSRR) is an important parameter to measure the noise immunity of a voltage reference. Conventional solutions to improve PSRR are at the cost of chip area and power consumption [5], such as additional amplifiers, long channel transistors, cascode structures [6], additional gain stage [7], and so on. Active attenuator and impedance adapting compensation were adopted in [8] to improve the PSRR at low and high frequencies, respectively. Yue et al. [9] used cascode current mirrors to enhance PSRR. Body bias and negative feedback techniques were utilized in [10] for high PSRR.
In order to overcome the abovementioned issues, an improved selfbiased BGR with high PSRR is proposed in this brief. Two feedback loops are realized at the same time for PSRR enhancement, which form a local negative feedback loop (LNFL) and a global selfbiased loop (GSBL). Meanwhile, a selfbias current source (SBCS) for the whole BGR is achieved. At steady state, the proposed BGR is selfpowered through the GSBL without additional bias current modules and chip area. The presented technique separates the supply voltage from the output reference voltage through a current amplifier embedded in GSBL, which can effectively improve the PSRR. In addition, in order to prevent the output voltage from instability, a LNFL is designed at the output voltage terminal to keep the output voltage stable. What is more, the temperaturestable reference voltage is generated with LNFL and GSBL in a multiplexing way. With these methods, a selfbiased BGR with high PSRR enhancement is implemented with compacted structure and current consumption.
Method
As shown in Fig. 1, the proposed BGR circuit consists of a startup circuit, a current amplifier, an operational amplifier, and a bandgap reference core. The startup circuit is used to get rid of the zerodegenerate point. The builtin offset voltage in the amplifier is set to be proportional to absolute temperature (PTAT) voltage, which can realize a PTAT current through resistor R1. With the positive TC of voltage across R1 and R2, the negative TC of V_{BE(Q5)} and V_{BE(Q4)} can be properly canceled to achieve a temperaturestable reference voltage at node V_{REF}. At the same time, a LNFL formed with the help of an amplifier to improve the performance. Combined with the current amplifier on the top of Fig. 1, a GSBL is realized for further PSRR improvement. The detail implementation of the proposed BGR is shown in Fig. 2.
Startup Circuit
The startup circuit is shown in the left part of Fig. 2. At the beginning of the startup stage, output voltage V_{REF} is at low level, which keeps MN8 and MN9 off. The current through MP1_1 is used to generate a startup current to MP5, where MP1_1 is as a large resistance with quite small aspect ratio. The voltage at V_{REF} will be gradually charged by the startup current. When the voltage at V_{REF} exceeds the minimum operation voltage of the bandgap core part, the bias current for the amplifier will be generated. This will drive the BGR to the desired operation point. At the same time, transistors MN8 and MN9 will be gradually on, which switches the supply current of MP5 to the selfbiased current generated in the bandgap core. After the startup is completed, the startup current is not turned off for V_{REF} readjustment in the case of reference voltage falling for some reasons [11].
SBCS Generator
There are two SBCS loops in the proposed BGR, which are helpful for performance enhancement [1]. The first one is located at the tail current of the amplifier. The PTAT current through transistor Q4 is mirrored into Q3. However, the current through Q4 is determined by the voltage across resistor R1, which is clamped to the input offset voltage of the amplifier. Due to the same aspect ratios of MP7 and MP8, the input offset voltage of the amplifier can be expressed as
where N is the area ratio of Q1 and Q2, and V_{T} is the thermal voltage. Therefore, the current in amplifier and bandgap core parts is PTAT current, which can be given by
The current of bandgap reference core is mirrored into the amplifier as tail current, forming the first selfbiased loop.
The second SBCS loop is made up with the current amplifier. The PATA current shown in equation (2) is mirrored into the current amplifier by the current mirror of MP7 and MP6. Then the current, I, is amplified by K as the current source to node VREF, which can be described as
where k_{1} = S_{MN6}/S_{MN7}, k_{2} = S_{MP3}/S_{MP2}, S_{i} is the aspect ratio of transistor i. Therefore, the current, KI, is reinjected into the amplifier and bandgap core parts, which constructs the second selfbias loop.
In order to guarantee the proper operation with low power consumption, the current, KI, should be slightly larger than the minimum current requirement of amplifier and bandgap core. In the proposed design, the currents through MP6, MP7, and MP8 are set at the same level, I. The current through bandgap core is 2I. Therefore, the relationship, 6 ≥ K > 5, should be satisfied [12,13,14].
V_{REF} Generator Circuit
The V_{REF} generator circuit is shown in the right part of Fig. 2, which consists of an amplifier and bandgap core. As shown in equation (2), the PTAT offset voltage of the amplifier is multiplexed by the SBCS loops [15]. This makes the current through R1, R2, and R_{Trimming} is PTAT current, which is used as temperature compensation of the negative TC of Q4 and Q5. The generated reference voltage, V_{REF}, can be expressed as
With the ratio adjustment of (R_{2} + R_{Trim min g})/R_{1}, a temperaturecompensated reference voltage can be realized with lowtemperature drift.
Feedback
A LNFL is established in the amplifier and bandgap core, which is formed by two small LNFLs. The first one, loop1, is from the input of the amplifier to V_{REF}, and feedback to the input of the amplifier. The other one, loop2, is from V_{REF} through Bandgap core to current tail of amplifier, and feedback to V_{REF}. For loop1, there are positive feedback and negative feedback double local loops with the input of the amplifier. The positive feedback loop is composed of Q5, R2, R1, Q1, MP8, and MX. The negative feedback loop consists of Q5, R2, Q2, and MX. The gain of the positive and negative feedback loop is derived as
where g_{m, Q1} is the transconductance of transistor Q1, r_{o, MP8} is the output resistance of transistor MP8, and the g_{m} of Q1 and Q2 is approximately equal. Since the effect of the negative feedback loop is stronger than that of the positive feedback loop, the loop1 behaves as a feedback loop, whose loop characteristic can be expressed as
where p_{0} is the dominant pole. With regard to loop2, the performance can be given by
where g_{m, MP8} is the transconductance of transistor MP8, and p_{1} is the dominant pole. As a result, the total loop gain of LNFL is
Taken equation (2) into consideration, equation (11) can be rewritten as,
where z_{0} ≈ g_{m, MP8}/[C_{1}(1 + 1/ ln N)]. Since N = 8 in the proposed design, it makes the zero, z_{0}, proximately equal to twice the pole, p_{1}, which can extend the loop bandwidth of LNFL by twice.
A GSBL is formed by the current amplifier, bandgap core, and amplifier, which can provide bias current for the whole circuit in a selfbiased method with enhanced PSRR performance. The loop gain of GSBL can be given by
where g_{m, MX} is the transconductance of transistor M_{X}. The main effect of transistor M_{X} is to lower the equivalent impedance at V_{REF} with the convenience of loop compensation. T_{GSBL} is set to be smaller than one in the proposed design, which can avoid oscillation.
With the help of LNFL and GSBL, the stability of generated reference voltage, V_{REF}, can be greatly improved.
PSRR of Proposed Voltage Reference
In order to simplify the PSRR calculation of the proposed circuit, the equivalent resistance of the part powered by the reference voltage, V_{REF}, is firstly calculated. The calculation diagram of this part is shown in Fig. 3 [16].
Figure 4a shows a smallsignal model for the equivalent resistance calculation of circuit branches 1, 2, where currents I_{1} and I_{2} flow in Fig. 3, respectively. Then, the equivalent resistance, R_{eq1,2}, can be expressed as
where g_{m,Q1} and r_{o,Q1} are transconductance and output resistance of Q1, respectively; R_{eq4} is equivalent resistance of branch with I_{4}. Since the gate voltage of MP6 shown in Fig. 2 is determined by the drain voltage of MP7, the power supply noise attenuation (PSNA) at node M should be also calculated, which can be given by
where r_{o,MP8} and r_{o,Q2} are output resistance of MP8 and Q2, respectively; g_{m,MP7} is transconductance of MP7. As claimed in equation (15), the supply noise has little influence on the sourcegate voltage of MP6. This makes MP6 act as a high impedance, r_{o,MP6}, which separates the noise impacts from the amplifier and bandgap core parts.
The equivalent resistance of branch with I_{3} in Fig. 3 can be derived by Fig. 4b, which can be expressed as
where g_{m,Mx} is the transconductance of Mx. The smallsignal model of equivalent resistance of branch with I_{4} in Fig. 3 is shown in Fig. 4c, which is,
Therefore, the smallsignal equivalent resistance of amplifier and bandgap core parts in Fig. 3 is
Therefore, the total PSRR of the proposed voltage reference can be illustrated in Fig. 5. The PSRR can be given by
Since g_{m}r_{o} > > 1 is generally valid, the influence of power supply noise on the generated reference voltage is greatly suppressed.
Results and Discussion
The voltage reference is implemented in a 180 nm BCD process, whose layout is shown in Fig. 6, occupying a 0.05690 mm^{2} active area.
The simulated startup waveforms are shown in Fig. 7, which illustrates the transient procedure with the powersupplyvoltage establishment. When the supply voltage is small, the entire reference circuit is not fully operated, which means the startup branch current is very small and the reference voltage is maintained at zero. With the rising of power supply voltage, the generated reference voltage is firstly stable at approximately 2V_{BE} due to the abnormal operation of the amplifier part in Fig. 2. When the supply voltage increases above the minimum required supply voltage of proposed BGR, the core operational amplifier starts to work, and the reference voltage is quickly stabilized at the desired value. Besides, the startup current drops about to zero with a desired reference voltage, while the proposed SBCS taking the place of current supply with the GSBL. The power consumption of startup circuit accounts for a small part of that of the chip.
The temperature characteristics of the generated reference voltage, V_{REF}, are shown in Fig. 8. The voltage variation of V_{REF} in the range of −55 °C ~ 125 °C is 11.3 mV, where a TC of 25 ppm/°C is achieved.
Figure 9 demonstrates the line sensitivity (LS) of the reference output voltage. The proposed BGR can be successfully established over 3 V supply voltage, and V_{REF} variation is 0.2 mV within 3 5 V supply voltage. This means a good LS of 0.08‰/V is realized.
The improved PSRR performance is illustrated in Fig. 10, which has a PSRR of 76 dB agreeing with theoretical results in equation (19) at low frequencies and above 46 dB up to 1 MHz.
Conventional binary trimming method is suitable for the proposed BGR, which adopts an 8bit trimming for R_{Trimming}. This can realize a 9 mV/LSB trimming step. Table 1 shows the performance of trimmed voltage reference with 3 5 V supply voltage and −55 to 125 °C temperature range under difference process corners, which include typical, slow, and fast cases. As shown in Table 1, the temperature drift is within 0.6%, the LS is below 0.12‰/V, and PSRR is above 71 dB@10 Hz.
Table 2 gives the characteristic summary of the proposed voltage reference and the comparison with some previously reported voltage references. Since the proposed voltage reference is aiming at high supply stability, no highorder temperature compensation is utilized in this paper. Therefore, the TC of [11,12,13], which mainly focus on temperature or power optimization methods, is smaller than that of the proposed voltage reference. The TC of the proposed voltage reference can be further optimized with literature reported curvaturecompensation methods as needed. With the proposed compacted structure, LNFL and GSBL are realized with a temperatureindependent reference voltage at the same time, which has the best PSRR and LS performance in Table 2.
Conclusion
A compacted selfbiased BGR with high PSRR is presented in this paper. The PTAT voltage is implemented by an operational amplifier with asymmetrical input offset voltage, and the negative temperature voltage is superimposed to generate a reference output voltage. At the same time, two feedback loops, LNFL and GSBL, are realized with the same parts for temperature stability, which reduces the structural complexity. This leads to selfsufficiency of supply current and power supply sensitivity improvement with high PSRR.
Availability of Data and Materials
All data generated or analyzed during this study are included in this published article.
Abbreviations
 BGR:

Bandgap reference
 PSRR:

Power supply rejection ratio
 TC:

Temperature coefficient
 PTAT:

Proportional to absolute temperature
 LNFL:

Local negative feedback loop
References
 1.
Z. Zhou, Y. Shi, Z. Huang, P. Zhu, Y. Ma, Y. Wang, Z. Chen, X. Ming, B. Zhang. A 1.6V 25μA 5ppm/°C curvature compensated bandgap reference. IEEE Transactions on Circuits and Systems I: Regular Papers, 2012, 59(4): 677–684. DOI: https://doi.org/10.1109/TCSI.2011.2169732.
 2.
Wang RC, Lu WG, Zhao M, Niu YZ, Liu ZK, Zhang YC et al (2018) A sub1 ppm/degrees C currentmode CMOS bandgap reference with piecewise curvature compensation. IEEE Transactions on Circuits and Systems IRegular Papers. 65(3):904–913. https://doi.org/10.1109/TCSI.2017.2771801
 3.
G. Q. Zhu, Y. T. Yang, Q. D. Zhang. A 4.6ppm/degrees C highorder curvature compensated bandgap reference for BMIC. IEEE Transactions on Circuits and Systems IIExpress Briefs, 2019, 66(9): 14926. DOI: https://doi.org/10.1109/TCSII.2018.2889808.
 4.
C. J. Huang, Y. J. Lai, Y. J. O. Yang, et al. A 4.2 nW and 18 ppm/degrees C temperature coefficient leakagebased square root compensation (LSRC) CMOS voltage reference. IEEE Transactions on Circuits and Systems IIExpress Briefs, 2019, 66(5): 72832. DOI: https://doi.org/10.1109/TCSII.2019.2908284.
 5.
M. Lee and S. Chang. Implementation of a high PSRR low power CMOS bandgap voltage reference circuit. 2018 Progress in Electromagnetics Research Symposium (PIERSToyama), Toyama, 2018, pp. 21212128. DOI: https://doi.org/10.23919/PIERS.2018.8597799.
 6.
Tianlin Cao, Yan Han, Xiaopeng Liu, Hao Luo, Lu Liao and Hao Zhang. A 0.9V highPSRR bandgap with selfcascode current mirror. 2012 IEEE International Conference on Circuits and Systems (ICCAS), Kuala Lumpur, 2012, pp. 267271. DOI: https://doi.org/10.1109/ICCircuitsAndSystems.2012.6408273.
 7.
Wenguan Li, Ruohe Yao and Lifang Guo. A low power CMOS bandgap voltage reference with enhanced power supply rejection. 2009 IEEE 8th International Conference on ASIC, Changsha, Hunan, 2009, pp.300304. DOI: https://doi.org/10.1109/ASICON.2009.5351450.
 8.
J. Z. Jiang, W. Shu, J. S. Chang. A 5.6 ppm/degrees C temperature coefficient, 87dB PSRR, sub1V voltage reference in 65nm CMOS exploiting the zerotemperaturecoefficient point. IEEE Journal of SolidState Circuits, 2017, 52(3): 62333. DOI: https://doi.org/10.1109/JSSC.2016.2627544.
 9.
H. Yue, X. Sun, J. Liu, et al. 16.8/15.2 ppm/°C 81 nW high PSRR dualoutput voltage reference for portable biomedical application. Electronics, 2019, 8(2). DOI: https://doi.org/10.3390/electronics8020213.
 10.
Zeng YH, Li Y, Zhang X et al (2017) Ultralowpower, high PSRR CMOS voltage reference with negative feedback. IET Circuits Devices & Systems 11(6):535–542. https://doi.org/10.1049/ietcds.2016.0452
 11.
Lee KK, Lande TS, Häfliger PD (2015) A subμW bandgap reference circuit with an inherent curvaturecompensation property. IEEE Transactions on Circuits and Systems I: Regular Papers 62(1):1–9. https://doi.org/10.1109/TCSI.2014.2340553
 12.
Ji Y, Lee J, Kim B, Park H, Sim J (2019) A 192pW voltage reference generating bandgap–V_{th} with process and temperature dependence compensation. IEEE Journal of SolidState Circuits 54(12):3281–3291. https://doi.org/10.1109/JSSC.2019.2942356
 13.
Chen H, Lee C, Jheng S, Chen W, Lee B (2017) A sub1 ppm/°C precision bandgap reference with adjustedtemperaturecurvature compensation. IEEE Transactions on Circuits and Systems I: Regular Papers 64(6):1308–1317. https://doi.org/10.1109/TCSI.2017.2658186
 14.
B. Ma and F. Yu. A novel 1.2–V 4.5ppm/°C curvaturecompensated CMOS bandgap reference. IEEE Transactions on Circuits and Systems I: Regular Papers, 2014, vol. 61, no. 4, pp. 10261035. DOI: https://doi.org/10.1109/TCSI.2013.2286032.
 15.
L. Liu, X. Liao and J. Mu. A 3.6 μ V_{rms} noise, 3 ppm/°C TC bandgap reference with offset/noise suppression and fivepiece linear compensation. IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 10, pp. 37863796, 2019. DOI: https://doi.org/10.1109/TCSI.2019.2922652.
 16.
Zhou Z, Cao J, Wang Y et al (2019) A nanoscale lowpower resistorless voltage reference with high PSRR. Nanoscale Res Lett 14:33. https://doi.org/10.1186/s1167101928647
 17.
Zhou Z et al (2019) A resistorless highprecision compensated CMOS bandgap voltage reference. IEEE Transactions on Circuits and Systems I: Regular Papers 66(1):428–437. https://doi.org/10.1109/TCSI.2018.2857821
 18.
Lee I, Sylvester D, Blaauw D (2017) A subthreshold voltage reference with scalable output voltage for lowpower IoT systems. IEEE J. SolidState Circuits 52(5):1443–1449. https://doi.org/10.1109/JSSC.2017.2654326
 19.
Wang L, Zhan C, Tang J, Liu Y, Li G (2018) A 0.9V 33.7ppm/°C 85nW subbandgap voltage reference consisting of subthreshold MOSFETs and single BJT. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26(10):2190–2194. https://doi.org/10.1109/TVLSI.2018.2836331
 20.
J. H. Duan, Z. Y. Zhu, J. L. Deng, et al. A novel 0.8V 79nW CMOSonly voltage reference with55dB PSRR @ 100 Hz. IEEE Transactions on Circuits and Systems IIExpress Briefs, 2018, 65(7): 84953. DOI: https://doi.org/10.1109/TCSII.2017.2728700.
Acknowledgements
Not applicable.
Funding
This work was supported by the National Science Foundation of China under Grant No. 61674025, and Open Projects of Sichuan Key Laboratory of Meteorological Information and Signal Processing under grant no. QXXCSYS201603.
Author information
Affiliations
Contributions
Yue Shi proposed the novel structure and was a major contributor in writing the manuscript. Shilei Li verified the theory with simulation and was a contributor in writing the manuscript. Jianwen Cao improved the design of the circuit. Other authors offered comments and revised the manuscript. All authors read and approved the final manuscript.
Corresponding author
Correspondence to Zekun Zhou.
Ethics declarations
Competing Interests
The authors declare that they have no competing interests.
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit http://creativecommons.org/licenses/by/4.0/.
About this article
Cite this article
Shi, Y., Li, S., Cao, J. et al. A 180 nm Selfbiased Bandgap Reference with High PSRR Enhancement. Nanoscale Res Lett 15, 104 (2020). https://doi.org/10.1186/s1167102003333w
Received:
Accepted:
Published:
Keywords
 Global selfbiased loop
 Local negative feedback loop
 High power supply rejection ratio