Fig. 8From: Simulation Study of the Double-Gate Tunnel Field-Effect Transistor with Step Channel ThicknessFabrication process of the SC TFET. a Silicon substrate preparation with SiN and photoresist deposition. b Etching, implantation, and annealing. c Isolation oxide deposition. d Reducing the thickness and width of SiN by ashing and trimming. e The step channel thickness is introduced. f Gate oxide forming, gate deposition, gate planarization, and source region implantationBack to article page