Fig. 3From: Robust and Latch-Up-Immune LVTSCR Device with an Embedded PMOSFET for ESD Protection in a 28-nm CMOS ProcessTCAD-simulated electrostatic potential distributions of a the proposed EP-LVTSCR and b the conventional LVTSCR at t = 5 ns under a 1.2A-TLP stressBack to article page