Fig. 4From: Growth and Selective Etch of Phosphorus-Doped Silicon/Silicon–Germanium Multilayers Structures for Vertical Transistors ApplicationSchematic diagrams of a doping strategy of changing growth chemistry, b experimental structure of Si/SiGe/Si MLs. The SiGe layer was grown with DCS. The purge time was 5 min with flow of 60 sccm after doped Si. The undoped Si spacer layer was 5 nm between bottom-doped Si and undoped SiGe. c Ge/Si profile and P concentration of P-doped Si/Si0.7Ge0.3/P-doped Si MLsBack to article page