Table 1 Adopted device parameters

Body thickness (T)

100 nm

Gate oxide thickness (\(t_{{{\text{ox}}}}\))

1 nm

The thickness of the tunnel region (\(t_{i}\))

0.5 nm

The entire width of the proposed B-TFET (W)

13 nm

The length of the S/D interchangeable regions (L_S/D)

8 nm

S/D region width (W_S/D)

8 nm

N +-doped region length (L_N+)

From 2 to 160 nm

The length of the intrinsic region between N⁺-doped region and P⁺-doped region (\(L_{i}\))

From 4 to 100 nm

The thickness of the buried oxide layer

50 nm

Doping concentration of P⁺ region (\(N_{A}\))

From \(5 \times 10^{18}\) to \(1 \times 10^{21} \,{\text{cm}}^{ - 3}\)

Doping concentration of N⁺ region (\(N_{D}\))

From \(5 \times 10^{18}\) to \(1 \times 10^{21} \,{\text{cm}}^{ - 3}\)

Drain to source voltage (\(V_{{{\text{ds}}}}\))

0.5 V

Gate to source voltage (\(V_{{{\text{gs}}}}\))

From − 0.4 to 1 V