Skip to main content

1.3 kV Vertical GaN-Based Trench MOSFETs on 4-Inch Free Standing GaN Wafer


In this work, a vertical gallium nitride (GaN)-based trench MOSFET on 4-inch free-standing GaN substrate is presented with threshold voltage of 3.15 V, specific on-resistance of 1.93 mΩ·cm2, breakdown voltage of 1306 V, and figure of merit of 0.88 GW/cm2. High-quality and stable MOS interface is obtained through two-step process, including simple acid cleaning and a following (NH4)2S passivation. Based on the calibration with experiment, the simulation results of physical model are consistent well with the experiment data in transfer, output, and breakdown characteristic curves, which demonstrate the validity of the simulation data obtained by Silvaco technology computer aided design (Silvaco TCAD). The mechanisms of on-state and breakdown are thoroughly studied using Silvaco TCAD physical model. The device parameters, including n-GaN drift layer, p-GaN channel layer and gate dielectric layer, are systematically designed for optimization. This comprehensive analysis and optimization on the vertical GaN-based trench MOSFETs provide significant guide for vertical GaN-based high power applications.


Wide-bandgap GaN-based power devices have been regarded as the great potential candidates for the next generation efficient power electronics and compact power systems, owing to the superior material properties such as high electron mobility, large breakdown field strength and high thermal stability [1,2,3,4,5]. Compared with high electron mobility transistors (HEMTs) [6,7,8,9,10,11] and current aperture vertical electron transistors (CAVETs) [12,13,14,15], GaN-based trench metal oxide semiconductor field effect transistors (MOSFETs) [16,17,18] are more competitive to realize intrinsically normally-off operation with higher current density, lower specific on-resistance (Ron,sp) and lower current collapse. Moreover, GaN-based trench MOSFETs possess relatively simple manufacturing process and do not need the regrowth of AlGaN/GaN layers [19, 20].

The development of lateral GaN-based MOSFETs has approximately come to saturation, due to the breakdown voltage (VBR) limited by the length of lateral drift region. Although the growth of length can increase VBR, the size of device enlarges, leading to reduction of the effective current density per unit chip area. In contrast, vertical GaN-based devices have been fully advanced. Under the same required VBR and amperage rating, smaller size and less cost can be realized on vertical GaN-based MOSFETs when make a contrast with lateral GaN MOSFETs [21]. In comparison with Si, Sapphire, SiC and Diamond substrate, the MOSFETs on free-standing GaN substrate can greatly reduce the probability of the high-density trap states and non-linearity contributed by lattice mismatch while operating at high power [22].

More studies have made great progress in VBR, Ron,sp and device reliability for GaN vertical MOSFETs in recent years. Floating P-body had been introduced in the N-GaN drift region to form “P-body/N-drift” junction via TCAD simulation for the improvement of VBR of the enhancement-mode vertical GaN MOSFET [23]. Vertical GaN interlayer-based trench MOSFET (OG-FET) on a large-area in-situ oxide performed threshold voltage (Vth) of 2.5 V, Ron,sp of 0.98 mΩ·cm2 and VBR of 700 V with regrown 10-nm unintentional-doped-GaN interlayer as the channel and 50-nm in-situ Al2O3 as the gate dielectric [24]. Vertical GaN trench-MOSFETs with MBE regrown UID-GaN channel were investigated, which avoided the need to reactivate the buried body p-GaN and promised the same benefit on channel mobility compared to the MOCVD regrowth [25]. The device characteristics had been improved for vertical GaN trench MOSFETs by using Silvaco ATLAS 2-D simulation in order to get the best trade-off between VBR and Ron,sp [26].

In this work, we present vertical GaN-based trench gate MOSFETs (GaN TG-MOSFETs) on 4-inch free-standing GaN substrate exhibiting normally off operation for high power applications. We use Silvaco TCAD to simulate the structure and performance of GaN TG-MOSFETs based on semiconductor physics and advanced process. The simulation results obtained by Silvaco ATLAS simulation are consistent well with experiment data on the characteristic curves of transfer, output, and breakdown voltage, respectively. The device parameters are researched comprehensively by using TCAD for providing guide in actual fabrication and optimization. The design of the parameters includes the thickness of n-GaN drift body layer (Ldrift), n-GaN drift trench region (Ltrench), p-GaN channel layer (Lchannel) and gate dielectric layer (Ldielectric). The doping density of p-GaN channel layer (Na) and n-GaN Drift layer (Nd) are included.

Experiment and Simulation Approach

High-quality, large-size and less-expensive GaN substrates are crucial for the progress of vertical GaN power devices. More techniques were proposed to optimize the growth of bulk GaN crystals, such as halide vapor phase epitaxy (HVPE), high nitrogen pressure solution (HNPS), basic and acidic ammonothermal, Na-flux method and near atmospheric pressure solution growth [27, 28]. HVPE is the main method for mass fabrication of GaN crystals, due to its high grow rate, high purity, high process repeatability and easy doping. The transparent 4-inch freestanding GaN wafer grown by HVPE with 13 points position for test is shown in Fig. 1a. We utilized a 420-μm-thick free-standing n+-GaN substrate in the device fabrication with the average mobility of 614 cm2·V−1·s−1 and the average dislocation density of 1.94 × 106 cm−2 at the top surface, as determined by contactless Hall measurement and cathodoluminescence (CL). The test result and CL image of the epitaxial layer are presented in Fig. 1b, c, respectively.

Fig. 1
figure 1

a Photograph of 4-inch freestanding GaN wafer, where the letters SZU can be clearly seen. b The mobility of GaN wafer. c The dislocation density and CL image of the epitaxial layer. d The fabrication process. e The schematic of energy band lined-up at the Al2O3/GaN heterointerface. f 3D drawing structure and g micrograph of the fabricated GaN TG-MOSFET

The fabrication process of the GaN TG-MOSFETs discussed in this work is shown in Fig. 1d. The epitaxial growth began with 12-µm lightly doped 8.0 × 1015 cm−3 n-GaN as the drift region. A 1.0-µm heavily doped p-GaN with a doping density of 1.0 × 1018 cm−3 was deposited as the channel region. Thereafter, a 0.2-µm-thick heavily doped n+-GaN with a doping density of 3 × 1018 cm−3 was grown as the source contact layer. The device fabrication process started with the formation of 0.2-μm-deep vertical trench and 1.7-μm-deep vertical mesa for p-body and gate contacts by using Cl2-based gases in reactive ion etching (RIE) at 15 W power, respectively. A 16-nm-thick Al2O3 film was deposited by atomic layer deposition (ALD) as gate dielectric. High-quality and stable MOS interface with low-density trap states is essential for GaN TG-MOSFETs. A two-step process, including simple acid cleaning and a following (NH4)2S passivation, was required to drastically reduce the interface states and border traps [29]. The source and drain electrodes with Ti/Al were annealed at 550 °C for 5 min in N2 ambient for ohmic contacts. The gate and p-body electrodes were composed of Ti/Au and Palladium, respectively. A 400-nm-thick SiO2 film was deposited by plasma enhanced chemical vapor deposition (PECVD) as the passivated isolation mesa. Finally, field plate termination was employed to impair the peak electric field crowded at the edge of PN junction around the isolation mesa. The Al-based field plate was connected to the source electrode.

The schematic of energy band lined-up at the Al2O3/GaN heterointerface in Fig. 1e. The forbidden band of GaN was exactly contained in that of Al2O3, where the deviations of the conduction band and valence band were 3.38 eV and 0.22 eV, respectively. It revealed that Al2O3 could maintain excellent insulation with GaN for electrons, which greatly reduced gate leakage current and improved device performance. The 3D drawing structure and parameters needed for optimization are shown in Fig. 1f. Figure 1g shows the micrograph of the device. The hexagonal crystal structure contained the outward vertical C axis, three horizontal axes a1, a2 and a3, and crystal planes in various directions.

The physical simulation models concerned for simulation were the parallel electric field-dependent mobility model, concentration-dependent mobility model, low field mobility model, Shockley–Read–Hall recombination model, Auger recombination model, impact ionization model, energy bandgap narrowing model and trap model [26, 29,30,31]. The main physical models and parameter values for simulation are shown in Table 1.

Table 1 The main model and parameter values for TCAD simulation

For GaN simulation, Si donors and Mg acceptors were not completely ionized at room temperature since their high activation energies, especially for Mg-doped p-type GaN [32,33,34]. Thus, according to Fermi–Dirac distribution, the incomplete ionization model was incorporated in the simulation for accurately reproducing the breakdown voltage. The ionized donors and acceptors impurity concentrations were given as follows

$$N_{D}^{ + } = \frac{{N_{D} }}{{1 + g_{D} \cdot \exp (\frac{{\varepsilon_{Fn} + E_{D,0} - \theta_{n} \cdot \sqrt[3]{{N_{D}^{{}} }} - E_{C} }}{KT})}}$$
$$N_{A}^{ - } = \frac{{N_{A} }}{{1 + g_{A} \cdot \exp (\frac{{E_{V} + E_{A,0} - \theta_{p} \cdot \sqrt[3]{{N_{A}^{{}} }} - \varepsilon_{Fp} }}{KT})}}$$

Here, gD and gA are the appropriate degeneracy factors for conduction and valence bands. ED,0 and EA,0 are the donor and acceptor ionization energy at very low doping levels. θn and θp are constants accounting for geometrical factors as well as for the properties of the material. Low field mobility model is the result of fitting Caughey Thomas like model to Monte Carlo data [26, 32]. It can be defined as

$$\begin{aligned} \mu_{(n/p)} (T,N) & = \mu_{1(n/p)} \cdot (T/300)^{{\beta_{1(n/p)} }} + \\ & \frac{{(\mu_{2(n/p)} - \mu_{1(n/p)} ) \cdot (T/300)^{{\beta_{2(n/p)} }} }}{{1 + [\frac{N}{{N_{ref(n/p)} \cdot (T/300)^{{^{{\beta_{3(n/p)} }} }} }}]^{{\rho_{(n/p)} \cdot (T/300)^{{^{{^{{\beta_{4(n/p)} }} }} }} }} }} \\ \end{aligned}$$

where µ1, µ2 are the minimum and maximum mobility, ρ, β1, β2, β3, β4, are all temperature dependent fitting parameters, Nref is the reference doping level and N is the donor concentration.

The Poisson’s equations and Current continuity equation were essential for the analysis of simulation [35]. As in semiconductor PN junction, avalanche breakdown occurred when the impact ionization integral reached unity

$$I_{n} = \int {\alpha_{n} \exp \left(\int_{{}}^{w} {\alpha_{p} - \alpha_{n} {\text{d}}v} \right)} {\text{d}}w = 1$$

where In is the impact ionization integral of electrons. The utilized ionization rate model of electrons and holes are variation of the classical Chynoweth model [36], which based upon the following expressions,

$$\alpha_{n} = AN \cdot \exp \left[ { - \left( \frac{BN}{E} \right)^{BETAN} } \right]$$
$$\alpha_{p} = AP \cdot \exp \left[ { - \left( \frac{BP}{E} \right)^{BETAP} } \right]$$

Here, E is the electric field in the direction of current flow at the p-GaN channel layer in the structure. Various group has reported impact ionization coefficients to accurately predict the breakdown of GaN power devices in recent years [37,38,39,40,41]. The coefficients AN, AP, BN, BP, BETAN and BETAP of the impact ionization model in this work were determined by referring to the experiments above.

In this study, the work was mainly carried out by TCAD. The data obtained by simulation had been calibrated with the result of experiment on GaN TG-MOSFET shown in the third part. The comprehensive analysis and optimization design on Ldrift, Ltrench, Ldielectric, Lchannel, Na and Nd of devices were demonstrated in the fourth part, respectively.

Results and Discussion

The initial device parameters of simulation model were set as follows: Nd = 8.0 × 1015 cm−3, Na = 1.0 × 1018 cm−3, Ldrift = 12 μm, Ltrench = 0.5 μm, Lchannel = 1.0 μm, and Ldielectric = 16 nm. The interface state could capture the free electrons in the channel and formed the negative interface charge, leading to the decrease of the number of free electrons and the increase of Ron,sp. A low density of interface state was beneficial to reduce Ron,sp and switch loss. The interface state in the simulation was defined as 1011 cm−2·eV−1 by referring to the previous work [25]. The characteristic curves of transfer, output, and breakdown of GaN TG-MOSFET via experiment (Exp) and simulation (Sim) are shown in Fig. 2, respectively. This simulation results were consistent well with the data of experiment, which could verify the validity of the results obtained by simulation and calibrate the simulation model.

Fig. 2
figure 2

a Transfer IV characteristics (IDVG) at VDS = 0.5 V. b Output IV characteristics (IDVD) at VGS = 0 V, 5 V, 10 V, 15 V and 20 V, respectively. c Off-state IV characteristics measured at VG = 0 V for fabricated GaN TG-MOSFET

Figure 2a shows the IDVG characteristics at VDS = 0.5 V. Several extraction methods were used to determine the value of Vth from the measured IDVG characteristics [42]. Normally-off operation with Vth (defined at IDS = 1 μA/mm) of 3.15 V was observed. Figure 3a shows the current could not be conducted between the source and drain, since the channel was not yet formed a conduction path. In Fig. 3b, the inversion layer of electron was effectively generated in the channel only when VGS > Vth, hence generating the drain-to-source current. The distributions of energy band along line A and line B during off-state and on-state are shown in Fig. 3c and Fig. 3d, respectively. From off-state to on-state, the energy of conduction band (CB) obviously reduced until closing to the Quasi-Fermi level (QFL). Therefore, electrons could easily jump to CB and generate conduction current. Figure 2b exhibits the output IV characteristics at VGS = 0 V, 5 V, 10 V, 15 V and 20 V, respectively. The Ron,sp estimated from the linear region was 1.93 mΩ·cm2 at VDS = 0.5 V and VGS = 20 V.

Fig. 3
figure 3

Electron concentration distributed at a VGS = 0 V, VDS = 0.5 V (off-state) and b VGS = 20 V, VDS = 0.5 V (on-state). The energy band distributed during c off-state and d on-state

Figure 2c demonstrates the off-state IV characteristics measured at VGS = 0 V. This work achieved the hard breakdown VBR of 1306 V when IDS > 50 mA/cm2 from experiment, while the VBR of simulation reached 2278 V. The insufficient activation of the Mg dopant existing in the p-GaN was considered as the reason for making the discrepancy in VBR between experiment and simulation. Finally, the corresponding figure of merit (FOM) obtained were 0.88 GW/cm2 and 1.68 GW/cm2 by experiment and simulation, respectively.

Two breakdown mechanisms, namely punch-through breakdown and avalanche breakdown, existed in the device, which were dominated by the product of Lchannel and Na (Lchannel · Na) of p-GaN. Taking the Na = 2.0 × 1017 cm−3 and various Lchannel for example by simulation as shown in Fig. 4a. Punch-through breakdown would occur when Lchannel · Na was lower than a certain value, such as Lchannel = 0.6 μm and Na = 2.0 × 1017 cm−3 in Fig. 4a. However, it would be changed to avalanche breakdown when Lchannel · Na was high enough, such as Lchannel = 0.8 μm and Na = 2.0 × 1017 cm−3. Moreover, the breakdown mechansims were studied in detail from the expansion of depletion region (DR), distributions of electric field and impact gen rate (IGR). Figure 4b shows the schematic of the device. Figures 4c–f and 5a–f show the expansion of DR of device with Lchannel = 0.4 μm and Lchannel = 1.2 μm, respectively. As drain voltage enlarged, the DR extended continually and was oriented toward the drain, which offered strong current blocking capability and suppressed the permature breakdown.

Fig. 4
figure 4

a Breakdown curves under Na = 2.0 × 1017 cm−3 and various Lchannel. b Schematic of GaN TG-MOSFET. cf Depletion region at different reverse bias under Na = 2.0 × 1017 cm−3 and Lchannel = 0.4 μm, including VDS = 200 V, 400 V, 800 V and 1000 V. g Electric Field distributed along line A at VDS = 1000 V

Fig. 5
figure 5

af Depletion region at different reverse bias under Na = 2.0 × 1017 cm−3 and Lchannel = 1.2 μm, including VDS = 200 V, 400 V, 800 V, 1000 V, 1500 V and 2000 V. g Electric Field distributed along line B at VDS = 2000 V

Punch-through breakdown occured in the device with Na = 2.0 × 1017 cm−3 and Lchannel = 0.4 μm when VDS > 1000 V for Lchannel · Na was low. The EF along line A is shown in Fig. 4g. The peak EF was ~ 2.3 MV/cm and did not reach the critical electric field strength value of GaN. A high potential barrier prevents current flow. The barrier between source and drain significantly reduced for the expansion of DR when VDS increased. Since the current was an exponential function of barrier height, the current increased rapidly once the punch-through condition was satisfied. The number of electrons injected from source region into channel had greatly increased through EF. Large current flowed from drain directly to source as shown in Fig. 6a. In Fig. 6b, the peak IGR was located at the reverse biased PN junction between p-GaN and n-GaN drift region as shown in the red circle.

Fig. 6
figure 6

a, b were the distributions of Total Current Density and Impact Gen Rate under Na = 2.0 × 1017 cm−3 and Lchannel = 0.4 μm, respectively. c, d were the distributions of Total Current Density and Impact Gen Rate under Na = 2.0 × 1017 cm−3 and Lchannel = 1.2 μm, respectively

Avalanche breakdown happened in the device with Na = 2.0 × 1017 cm−3 and Lchannel = 1.2 μm when VDS > 2000 V for the Lchannel · Na was high. The EF along line B is shown in Fig. 5g. The peak EF was ~ 3.45 MV/cm and closed to the critical electric field of 3.3 MV/cm of GaN. The energy of electrons and holes was enhanced by EF when they pass through the space charge region. Since they collided with electrons of atoms in DR, large numbers of new electron–hole pairs were generated, causing the avalanche effect. Large electron and hole current were produced as shown in Fig. 6c. The electron current mainly flowed to drain, while hole current flowed to the source along p-GaN region. In the red circle of Fig. 6d, the peak IGR was located at the gate corner. It implied that the breakdown characteristic was similar to that of PN junction diode as long as punch-through did not occur. The simulation showed that device could achieve avalanche and avoid punch-through breakdown with enough value of Lchannel·Na. The effect of various Na on the breakdown mechanism was similar to that of Lchannel.

Analysis and Performance Evaluation

This simulation focused on studying the effects of various device parameters and obtaining the scheme of optimization design. Firstly, the thickness and doping density of n-GaN drift layer were researched with different initial values. Then, we analysed the thickness and doping density of p-GaN channel layer based on the optimal parameters of n-GaN drift layer. Finally, the impact of the thickness of gate dielectric was thoroughly studied. All the changes of the above parameters were discussed within a reasonable range. The power figure of merit FOM = VBR2/Ron,sp and Vth could be used as a criterion for optimization.

Analysis the Influence of n-GaN Drift Layer

As shown in Fig. 7a, VBR increased and saturated at a certain value as Ldrift increased with different initial conditions. The phenomenon that DR extended and saturated with the growth of Ldrift caused the VBR increased and saturated. Conversely, VBR decreased with the growth of Nd. The situation was equivalent to the effect of the doping concentration in the low-doped side of the PN single junction diode on the VBR, which demonstrated that the value of Nd was inversely proportional to VBR. It implied that VBR prematurely saturated at thin Ldrift with high Nd. Low Nd had larger DR than high Nd due to the IGR of electron was low. Large DR could withstand high voltage and prevent electron absorbing electric field energy to reach breakdown. The change of Ron,sp was mainly caused by the variation of Rdrift (Ron,sp of n-GaN drift layer). The Ron,sp decreased with the increase of Nd and decrease of Ldrift, respectively. Ron,sp decreased from 2.55 mΩ·cm2 to 1.56 mΩ·cm2 and VBR reduced from 2558 to 1997 V as Nd increased from 8.0 × 1015 cm−3 to 1.0 × 1016 cm−3 under Ldrift = 12 μm. In Fig. 7b, the obtained peak FOM were 2.76 GW/cm2, 2.69 GW/cm2 and 2.62 GW/cm2 under Ldrift = 16 μm, Ldrift = 12 μm, and Ldrift = 10 μm with the growth of Nd, respectively. It demonstrated that the optimal FOM could be obtained under the low Nd and thick Ldrift. In contrast, the change of Nd and Ldrift had no effect on Vth, and it remained at 3.15 V. The impact on Ron,sp and VBR were obvious by the change of Nd and Ldrift, while hardly influenced Vth.

Fig. 7
figure 7

a Simulated Ron,sp and VBR of the device versus Ldrift and Nd. b Vth and FOM as a function of Ldrift and Nd. c Simulated Ron,sp and VBR of the device versus Ltrench and Nd. d Vth and FOM as a function of Ltrench and Nd. In (a)–(d), the square, circle and triangle curves were simulated under Nd = 6.0 × 1015 cm−3, Nd = 8.0 × 1015 cm−3 and Nd = 1.0 × 1016 cm−3, respectively

With the increase of Ltrench from 0.1 to 1.0 µm in Fig. 7c, d, Ron,sp continuously decreased. In contrast, VBR and FOM first increased and then decreased as the advance of Ltrench, finally reaching peak value at Ltrench = 0.2 µm. The obtained peak FOM were 3.15 GW/cm2, 3.45 GW/cm2 and 3.64 GW/cm2 under Nd = 6.0 × 1015 cm−3, Nd = 8.0 × 1015 cm−3, and Nd = 1.0 × 1016 cm−3, respectively. The impact of Ltrench on FOM was apparent when it was thin. The variety of Nd and Ltrench also made little difference on Vth. Vth showed independence for the change of Nd, Ldrift and Ltrench, due to the p-type channel region.

Analysis the Impact of p-GaN Channal and Dielectric

The effects of the Lchannel and Na of p-GaN channel layer were investigated based on Ldrift = 12 μm and Ltrench = 0.2 μm of n-GaN drift layer. The change of Ron,sp was mainly caused by the variation of Rchannel (Ron,sp of p-GaN channel layer). The curves of Ron,sp showed continuous rising trend with the enhancement of Lchannel as shown in Fig. 8a. As Na increased from 2.0 × 1017 cm−3 to 3.0 × 1018 cm−3 under Lchannel = 1.0 μm, Ron,sp showed increasing trends from 1.94 mΩ·cm2 to 1.96 mΩ·cm2. The effect on the Ron,sp brought by the variety of Lchannel was little. The growth of Na could enlarge the VBR from 65 to 2632 V under 0.1 um. VBR increased and saturated at Lchannel = 0.8 μm under Na = 2.0 × 1017 cm−3. In contrast, VBR increased and saturated at Lchannel = 0.2 μm under Na = 8.0 × 1017 cm−3 and Na = 1.0 × 1018 cm−3, respectively. Moreover, VBR kept saturated from 0.1 μm to 1.0 μm of Lchannel under Na = 3.0 × 1018 cm−3. The high enough value of Lchannel · Na could achieve avalanche breakdown, which could be seen from the saturated VBR. On the contrary, the unsaturated VBR was known as punch-through breakdown. Similarly, the variation trend of FOM was the same as VBR. The peak FOM obtained was 3.59 GW/cm2. Vth grew from 1.19 V to 7.93 V under Lchannel = 1.0 μm with the increase of Na as shown in Fig. 8b. The change of Na had a marked effect on Vth, whereas the impact brought by the variety of Lchannel on Vth was negligible.

Fig. 8
figure 8

a Simulated Ron,sp and VBR of the device versus Lchannel and Na. b Vth and FOM as a function of Lchannel and Na. In (a) and (b), the square, rhombus, circle and triangle curves were simulated under Na = 2.0 × 1017 cm−3, Na = 8.0 × 1017 cm−3, Na = 1.0 × 1018 cm−3 and Na = 3.0 × 1018 cm−3, respectively. c Simulated Ron,sp and VBR of the device versus Ldielectric. d Vth and FOM as a function of Ldielectric

The impact of the Ldielectric was researched based on Lchannel = 1.0 μm. The growth of Ldielectric would reduce Cox and electron concentration of channel layer under on-state condition, resulting in larger Ron,sp and Vth. Ron,sp increased from 1.92 mΩ·cm2 to 2.24 mΩ·cm2 and Vth enhanced from 1.87 V to 8.97 V for Ldielectric increasing from 8 to 50 nm as shown in Fig. 8c, d. Ldielectric had no effect on VBR, leading to the reduction of FOM from 3.63 GW/cm2 to 3.10 GW/cm2.


In this work, we analysed the performance of the fabricated GaN TG-MOSFET on 4-inch free-standing GaN substrate by Silvaco TCAD. The mechanisms of on-state and breakdown have been well studied. The key device parameters have been thoroughly researched considering the trade-off between Ron,sp and VBR. The normally off operation and high breakdown voltage show enormous potential to provide a bright future application for vertical GaN-based high power electronics.

Availability of data and materials

All data generated or analyzed during this study are included within the article.


  1. Boutros KS, Chu R, Hughes B (2012) GaN power electronics for automotive application. IEEE Energytech 1–4

  2. Ueda T (2014) Recent advances and future prospects on GaN-based power devices. In: 2014 international power electronics conference (IPEC-Hiroshima 2014-ECCE ASIA):2075–2078

  3. Li H, Yao C, Fu L, Zhang X, Wang J (2016) Evaluations and applications of GaN HEMTs for power electronics. In: 2016 IEEE 8th international power electronics and motion control conference (IPEMC-ECCE Asia), pp 563–569

  4. Flack TJ, Pushpakaran BN, Bayne SB (2016) GaN technology for power electronic applications: a review. J Electron Mater 45(6):2673–2682

    Article  CAS  Google Scholar 

  5. Sun R, Lai J, Chen W, Zhang B (2020) GaN power integration for high frequency and high efficiency power applications: a review. IEEE Access 8:15529–15542

    Article  Google Scholar 

  6. Liu X, Kim Fong Low E, Pan J, Liu W, Leong Teo K, Tan LS, Yeo YC (2011) Impact of In situ vacuum anneal and SiH4 treatment on electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors. Appl Phys Lett 99(9):093504

    Article  Google Scholar 

  7. Liu X, Zhan C, Chan KW, Owen MHS, Liu W, Chi DZ, Tan LS, Chen KJ, Yeo YC (2013) AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors with a high breakdown voltage of 1400 V and a complementary metal–oxide–semiconductor compatible gold-free process. Jpn J Appl Phys 52(4S):04CF06

    Article  Google Scholar 

  8. Huang S, Liu X, Wang X, Kang X, Zhang J, Bao Q, Wei K, Zheng Y, Zhao C, Gao H (2016) High uniformity normally-OFF GaN MIS-HEMTs fabricated on ultra-thin-barrier AlGaN/GaN heterostructure. IEEE Electron Device Lett 37(12):1617–1620

    Article  CAS  Google Scholar 

  9. Liu S, Wang M, Tao M, Yin R, Gao J, Sun H, Lin W, Wen CP, Wang J, Wu W (2017) Gate-recessed normally-OFF GaN MOSHEMT with improved channel mobility and dynamic performance using AlN/Si3N4 as passivation and post gate-recess channel protection layers. IEEE Electron Device Lett 38(8):1075–1078

    Article  CAS  Google Scholar 

  10. Han PC, Yan ZZ, Wu CH, Chang EY, Ho YH (2019) Recess-Free Normally-off GaN MIS-HEMT Fabricated on Ultra-Thin-Barrier AlGaN/GaN Heterostructure. In: 2019 31st international symposium on power semiconductor devices and ICs (ISPSD), pp 427–430

  11. Liu X, Chiu HC, Liu CH, Kao HL, Chiu CW, Wang HC, Ben J, He W, Huang CR (2020) Normally-off p-GaN gated AlGaN/GaN HEMTs using plasma oxidation technique in access region. IEEE J Electron Devices Soc 8:229–234

    Article  CAS  Google Scholar 

  12. Nie H, Diduck Q, Alvarez B, Edwards AP, Kayes BM, Zhang M, Ye G, Prunty T, Bour D, Kizilyalli IC (2014) 1.5-kV and 2.2-mΩ-cm2 Vertical GaN Transistors on Bulk-GaN Substrates. IEEE Electron Device Lett 35(9):939–941

    Article  CAS  Google Scholar 

  13. Ji D, Laurent MA, Agarwal A, Li W, Mandal S, Keller S, Chowdhury S (2016) Normally OFF trench CAVET with active Mg-doped GaN as current blocking layer. IEEE Trans Electron Devices 64(3):805–808

    Article  Google Scholar 

  14. Shibata D, Kajitani R, Ogawa M, Tanaka K, Tamura S, Hatsuda T, Ishida M, Ueda T (2016) 1.7 kV/1.0 mΩ·cm2 normally-off vertical GaN transistor on GaN substrate with regrown p-GaN/AlGaN/GaN semipolar gate structure. In: 2016 IEEE international electron devices meeting (IEDM).

  15. Ji D, Agarwal A, Li H, Li W, Keller S, Chowdhury S (2018) 880 V/2.7 mΩ·cm2 MIS Gate Trench CAVET on Bulk GaN Substrates. IEEE Electron Device Lett 39(6):863–865

    Article  CAS  Google Scholar 

  16. Oka T, Ueno Y, Ina T, Hasegawa K (2014) Vertical GaN-based trench metal oxide semiconductor field-effect transistors on a free-standing GaN substrate with blocking voltage of 1.6 kV. Appl Phys Express 7(2):21002–21002

    Article  CAS  Google Scholar 

  17. Oka T, Ina T, Ueno Y, Nishii J (2015) 1.8 mΩ·cm2 vertical GaN-based trench metal-oxide-semiconductor field-effect transistors on a free-standing GaN substrate for 1.2-kV-class operation. Appl Physics Express 8(5):54101–54101

    Article  Google Scholar 

  18. Li R, Cao Y, Chen M, Chu R (2016) 600 V/1.7 Ω normally-Off GaN vertical trench metal-oxide-semiconductor field-effect transistor. IEEE Electron Device Lett 37(11):1466–1469

    Article  CAS  Google Scholar 

  19. Williams RK, Darwish MN, Blanchard RA, Siemieniec R, Rutter P, Kawaguchi Y (2017) The trench power MOSFET: Part I-History, technology, and prospects. IEEE Trans Electron Devices 64(3):674–691

    Article  Google Scholar 

  20. Williams RK, Darwish MN, Blanchard RA, Siemieniec R, Rutter P, Kawaguchi Y (2017) The trench power MOSFET-part II: application specific VDMOS, LDMOS, packaging, and reliability. IEEE Trans Electron Devices 64(3):692–712

    Article  Google Scholar 

  21. Guo Z, Hitchcock C, Chow TSP (2019) Comparative performance evaluation of lateral and vertical GaN high-voltage power field-effect transistors. Jpn J Appl Phys 58(SC):9

    Google Scholar 

  22. Liu X, Gu H, Li K, Guo L, Zhu D, Lu Y, Wang J, Kuo HC, Liu Z, Liu W (2017) AlGaN/GaN high electron mobility transistors with a low sub-threshold swing on free-standing GaN wafer. AIP Adv 7(9):95305–95305

    Article  Google Scholar 

  23. Zhou Q, Wei D, Peng X, Zhu R, Dong C, Huang P, Wei P, Xiong W, Ma X, Dong Z (2018) A novel enhancement-mode GaN vertical MOSFET with double hetero-junction for threshold voltage modulation. Superlattices Microstruct 123:297–305

    Article  CAS  Google Scholar 

  24. Ji D, Gupta C, Agarwal A, Chan SH, Lund C, Li W, Keller S, Mishra UK, Chowdhury S (2018) Large-area in-situ oxide, GaN interlayer-based vertical trench MOSFET (OG-FET). IEEE Electron Device Lett 39(5):711–714

    Article  Google Scholar 

  25. Li W, Nomoto K, Lee K, Islam S, Hu Z, Zhu M, Gao X, Pilla M, Jena D, Xing HG (2018) Development of GaN vertical trench-MOSFET with MBE regrown channel. IEEE Trans Electron Devices 65(6):2558–2564

    Article  CAS  Google Scholar 

  26. Liu S, Song X, Zhang J, Zhao S, Luo J, Zhang H, Zhang Y, Zhang W, Zhou H, Liu Z (2020) Comprehensive Design of Device Parameters for GaN Vertical Trench MOSFETs. IEEE Access 8:57126–57135

    Article  Google Scholar 

  27. Kucharski R, Sochacki T, Lucznik B, Bockowski M (2020) Growth of bulk GaN crystals. J Appl Phys 128(5):050902

    Article  CAS  Google Scholar 

  28. Mikawa Y, Ishinabe T, Kagamitani Y, Mochizuki T, Ikeda H, Iso K, Takahashi T, Kubota K, Enatsu Y, Tsukada Y, Izumisawa S (2020) Recent progress of large size and low dislocation bulk GaN growth//Gallium Nitride Materials and Devices XV. Int Soc Opt Photon 11280:1128002

    Google Scholar 

  29. Ren B, Sumiya M, Liao M, Koide Y, Liu X, Shen Y, Sang L (2018) Interface trap characterization of Al2O3/GaN vertical-type MOS capacitors on GaN substrate with surface treatments. J Alloys Compd 767:600–605

    Article  CAS  Google Scholar 

  30. Park J, Lee JH (2016) A 650 V super-junction MOSFET with novel hexagonal structure for superior static performance and high BV resilience to charge imbalance: A TCAD simulation study. IEEE Electron Device Lett 38(1):111–114

    Article  Google Scholar 

  31. Huang H, Li F, Sun Z, Sun N, Zhang F, Cao Y, Zhang H, Tao P (2019) Gallium nitride normally-off vertical field-effect transistor featuring an additional back current blocking layer structure. Electronics 8(2):241–241

    Article  CAS  Google Scholar 

  32. Sabui G, Parbrook PJ, Arredondo-Arechavala M, Shen Z (2016) Modeling and simulation of bulk gallium nitride power semiconductor devices. AIP Adv 6(5):55006–55006

    Article  Google Scholar 

  33. Donato N, Udrea F (2018) Static and dynamic effects of the incomplete ionization in superjunction devices. IEEE Trans Electron Devices 65(10):4469–4475

    Article  CAS  Google Scholar 

  34. Mukherjee K, Santi CD, Buffolo M, Borga M, You S, Geens K, Bakeroot B, Decoutere S, Gerosa A, Meneghesso G (2021) Understanding the leakage mechanisms and breakdown limits of vertical GaN-on-Si p+nn diodes: the road to reliable vertical MOSFETs. Micromachines 12(4):445

    Article  Google Scholar 

  35. Tripathi PM, Soni H, Chaujar R, Kumar A (2020) Numerical simulation and parametric assessment of GaN buffered trench gate MOSFET for low power applications. IET Circuits Devices Syst 14:915–922

    Article  Google Scholar 

  36. Manual AU (2010) Silvaco. Santa Clara, CA.

  37. Oğuzman IH, Bellotti E, Brennan KF, Kolník J, Wang R, Ruden PP (1997) Theory of hole initiated impact ionization in bulk zincblende and wurtzite GaN. J Appl Phys 81(12):7827–7834

    Article  Google Scholar 

  38. Cao L, Wang J, Harden G, Ye H, Stillwell R, Hoffman AJ, Fay P (2018) Experimental characterization of impact ionization coefficients for electrons and holes in GaN grown on bulk GaN substrates. Appl Phys Lett 112(26):262103–262103

    Article  Google Scholar 

  39. Ji D, Ercan B, Chowdhury S (2019) Experimental determination of impact ionization coefficients of electrons and holes in gallium nitride using homojunction structures. Appl Phys Lett 115(7):73503

    Article  Google Scholar 

  40. Maeda T, Narita T, Yamada S, Kachi T, Kimoto T, Horita M, Suda J (2019) Impact ionization coefficients in GaN measured by above-and sub-Eg illuminations for p/n+ junction. In: 2019 IEEE international electron devices meeting (IEDM)

  41. Cooper JA, Morisette DT (2020) Performance limits of vertical unipolar power devices in GaN and 4H-SiC. IEEE Electron Device Lett 41(6):892–895

    Article  CAS  Google Scholar 

  42. Ortiz-Conde A, Sánchez FG, Liou JJ, Cerdeira A, Estrada M, Yue Y (2002) A review of recent MOSFET threshold voltage extraction methods. Microelectron Reliab 42:583–596

    Article  Google Scholar 

Download references


We thank the reviewers for their valuable comments.


This work was supported by National Natural Science Foundation of China (61974144, 62004127), Key-Area Research and Development Program of Guangdong Province 2020B010169001, Guangdong Science Foundation for Distinguished Young Scholars, and Science and Technology Foundation of Shenzhen JSGG20191129114216474.

Author information

Authors and Affiliations



XL and WH conceived the idea. ZL and JL did the experiment part of this work. JL and FL did the simulation part of this work. JW collected and sorted out the literatures. BW, MW, NL, H-CC, and H-CK took place in analysis and discussion. Jian Li drafted the manuscript. Xinnan Lin and Jingbo Li provided professional assistance in the revised manuscript. All authors read and approved the final manuscript.

Corresponding author

Correspondence to Xinke Liu.

Ethics declarations

Competing interests

The authors declare that they have no competing interests.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

He, W., Li, J., Liao, Z. et al. 1.3 kV Vertical GaN-Based Trench MOSFETs on 4-Inch Free Standing GaN Wafer. Nanoscale Res Lett 17, 14 (2022).

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI:


  • Free standing gallium nitride (GaN)
  • Trench MOSFET
  • Breakdown
  • TCAD