Background

The need for high density, high performance, and low power consumption has necessitated the development of novel memory devices. Because of their compact structure, non-destructive read-out operation, and multi-bit storage, non-volatile transistors such as ferroelectric field-effect transistors (FeFETs), floating-gate transistors, and IGZO memristors have attracted much attention for embedded memories, computing-in memory, and neuromorphic synapse applications [1,2,3,4,5]. The stimulus is applied to the gate electrode of the transistors for synaptic operation, and the drain side current is the post-synapse current [6, 7].

Recently, non-volatile field-effect transistors (NVFETs) utilizing amorphous Al2O3 and ZrO2 gate insulators were experimentally realized, which was attributed to the switchable polarization (P) induced by the voltage-modulation of the oxygen vacancy (\({V}_{\mathrm{O}}^{+}\))-related dipoles [8,9,10,11]. The mechanism of voltage-modulation of \({V}_{\mathrm{O}}^{+}\) in ferroelectric tunnel junctions was also demonstrated, which improved the tunneling electroresistance ratio of the device [12]. Compared to the polycrystalline doped-HfO2 FeFETs, NVFETs with amorphous dielectrics exhibited significantly lower operation voltage and better linearity for multi-threshold voltage operation [9]. These characteristics make them a promising candidate for low-power neuromorphic devices that closely mimic biological behaviors, which are not to be investigated yet.

In this work, biological synapse behaviors such as short-term plasticity (STP), long-term potentiation (LTP), the transition from short-term memory (STM) to long-term memory (LTM), and spike-timing-dependent plasticity (STDP) are emulated based on the single amorphous HfO2 NVFET, without using additional circuit elements.

Methods

The process flow in [9] was used to fabricate the NVFETs with an amorphous HfO2 gate insulator on 4-inch n-type Ge(001). After the pre-gate cleaning, the substrate was loaded into an atomic layer deposition (ALD) chamber to deposit the HfO2 at 300 °C. Then, a 100-nm-thick TaN gate electrode was deposited by the reactive sputtering. After the gate electrode patterning and etching, the source/drain (S/D) regions were implanted by BF2+. 20-nm thick nickel (Ni) S/D metal electrodes were formed by a lift-off process. Finally, the repaid thermal annealing (RTA) at 350 °C was carried out to improve the interface quality and form the Ni germanium silicide S/D contacts.

The schematic of the fabricated NVFET is shown in Fig. 1a. Figure 1b shows a 3-nm-thick amorphous HfO2 imaged with high-resolution transmission electron microscopy (HRTEM). Figure 1c depicts the measured ferroelectric-like P vs. voltage (V) behavior in the amorphous HfO2 capacitor at a frequency of 1 kHz. The underlying mechanism for the ferroelectric-like behaviors in this amorphous HfO2 devices is similar to that for those devices in Refs. [8, 9]. The extracted evolution of the remnant P (Pr) and coercive voltage (Vc) for the device during the endurance test is shown in Fig. 1d. No wake-up or imprint is observed over 106 cycles. A positive-up and negative-down (PUND) test is used to extract the switching current component of the device by isolating the non-switching charge (Fig. 1e), demonstrating the true P.

Fig. 1
figure 1

a Schematic of the NVFET with amorphous HfO2 gate insulator. b HRTEM image shows the 3-nm-thick amorphous HfO2. c Measured P–V curves for TaN/HfO2/Ge capacitor. d Pr and Vc vs. the number of sweeping cycles for amorphous HfO2 capacitors. e PUND test of HfO2 capacitor exhibiting the switching current component by isolating the non-switching charge

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Results and Discussion

In contrast to the trapping/detrapping process [13,14,15], a ferroelectric-like clockwise hysteresis loop is observed for the DC sweeping of the drain current (ID) as a function of gate voltage (VG) curves for the transistor with the amorphous HfO2 gate insulator, as shown in Fig. 2a. The non-volatile memory function is induced by the ferroelectric-like P switching in the gate stack. Figure 2b shows the initial ID–VG curve for the device and those underwent with 100 ns, 1 μs, 10 μs, 100 μs, and 1 ms write/erase (W/E) pules at ± 3 V voltage providing a non-volatile memory function, respectively. The device has a gate length (LG) of 3 μm and a gate width (W) of 80 μm. The write (erase) operation is achieved by applying positive (negative) voltage pulses to the gate of the HfO2 FET, to raise (lower) its threshold voltage (VTH).

Fig. 2
figure 2

a Dual-direction sweeping of ID-VG curves of the amorphous HfO2 NVFET. b Measured ID-VG curves of the device with ± 3 V W/E pulses, and the pulse width varies from 100 ns to 1 ms. c MW for the amorphous HfO2 NVFET with various pulse width. d Stable MW maintains after 106 W/E cycles underwent ± 3 V, 100 ns W/E pulses. e Several hundred seconds retention time was maintained of the amorphous HfO2 device

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Figure 2c plots the MW values for different W/E pulse widths. As the pulse width increases from 100 ns to 10 μs, the MW increases to 1.2 V; but when the W/E pulse width further increases, the MW decreases. Trapping/detrapping process is thought to cause the degradation of MW under the 100 μs to 1 ms W/E pulses. Here, MW is the VTH difference between the two states, and VTH is defined as VG at ID = 100 nA⋅W/LG.

As shown in Fig. 2d, a stable MW is maintained over 106 W/E cycles. Figure 2e shows that a stable MW of the amorphous HfO2 device can be maintained over several hundred seconds. The limitation retention time of the device is mainly due to the smaller Pr and large depolarization field. Recent studies have shown that the non-volatile devices with limited retention time can be alternative candidates for high-density and lower power DRAM architectures [16, 17].

Synapse is a basic unit of the human neural network to realize the information transmission from the pre-synaptic neuron to the post-synaptic neuron. The STP is a key factor that affects the biographic performance of the NVFET synapse in the neural system [18]. Figure 3 shows the STP characteristics of a HfO2 NVFET under the single VG pulse with a fixed pulse magnitude of -3 V. The VG pulse width varies from 1 μs to 10 ms and the base voltage varies from 0.5 V to − 1.5 V. As a three-terminal device, the STP performance can be modulated by changing the base voltage, magnitude, and width of the VG pulses. Underwent an applied VG stimulus, the post-synaptic ID of the device increases to a high ID state and decays to a low ID state when the VG pulse ended. For all the measurements, the devices are in the same relaxed pre-state.

Fig. 3
figure 3

Base voltage varies from 0.5 to -1.5 V. The widths of VG pulses in a–d are 1 μs, 100 μs, 1 ms, and 10 ms, respectively

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As shown in Fig. 3a, underwent a 1 μs VG pulse, the device exhibits a lower post-synaptic ID under the base voltage of − 1.5 V and − 1.0 V compared to the cases under 0 V and − 0.5 V VG base. It is speculated that this could be due to the smaller difference between base and pulse VG voltages. As the VG pulse is widened to ms, the post-synaptic ID no longer depends on the base voltage (Fig. 3c, d). In general, the post-synaptic ID of the device is improved with widening the stimulus VG pulse.

According to Fig. 3, there is a refractory period after the VG pulse. The ID barely varies with the VG, which accurately simulates the bio-synapse with the external stimulating signal. The refractory period of the NVFET synapse is approximately 10–100 μs, which does not depend on the VG pulse width or magnitude. Figure 4 depicts the post-synaptic ID of the transistor that underwent multiple VG input pulses within the refractory period. During this period, ID is excitable by the VG pulse, but its value is less than that for the initial pulse firing. After the refractory period, the post-synaptic ID increases with time to a saturate state, and values of post-synaptic ID in saturation increase with the decrease in the base voltage.

Fig. 4
figure 4

Post-synaptic ID of the device underwent multiple VG input pulses within the relative refractory period

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Besides the width and magnitude of the pulse, the stimulation rate also influences the memory formation of the device. To examine the effects of the stimulation rate on the transistor, the ten cycles (N = 10) of stimuli/read VG are applied to the gate electrode. As shown in Fig. 5a, during the stimuli or read, the amplitude and time of the VG pulse are fixed, and the cycle period T is changed by varying the interval parameter. The ID of the transistor was read at low voltage immediately after each stimulation pulse, which is denoted by I1, I2, …, I10 [19].

Fig. 5
figure 5

a VG pulse waveform with the different T. b The ID increase as a function of the gate stimulus number plots with the different T. c Extracted (I2 − I1)/I1 and (I10 − I1)/I1, representing PPF and PTP behaviors, respectively, of the transistor

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The dynamic change in the ID of the amorphous HfO2 NVFET under a series of VG pulses with the different T at a VDS of − 0.5 V is shown in Fig. 5b. The ID (i.e., ΔID/I1) of the device increases with the stimuli T numbers to mimic the memory behavior in the biological system. Here, ΔID is calculated by IN − I1, (N = 1, 2, …, 10). Note that the ID of the device increases, i.e., (ΔID/I1) with the reduced T. With a high stimulation rate being the most effective and a low stimulation rate being the least effective for transforming from STM to LTM.

Figure 5c plots the (I2 − I1)/I1 and (I10 − I1)/I1, which represent the experimental conditions for paired-pulse facilitation (PPF) and post-tetanic potentiation (PTP) used in biological studies, respectively [20, 21]. The PPF and PTP phenomena in our amorphous HfO2 synaptic transistor can be compared to synapses in biology. If be former, the synaptic response is enhanced when one stimulus is followed by the same stimulus soon after; if be latter, the synaptic transmission gradually increases with the number of stimuli when a series of stimuli are received [20,21,22]. These verify the feasibility of the amorphous HfO2 device in realizing the transformation of simulated biological memory. The error bars reflect the standard deviation when repeating the measurement a few times to prove the correctness of the data and minimize fluctuations in data.

The temporal relationship of activity between the pre- and post-synaptic neurons is another important aspect of the synapse. We define tPRE and tPOST as the arrival times of the pre-spike and the post-spike, respectively. The change in synaptic weight (Δw) is a function of the Δt (Δt = tPRE − tPOST) between pre- and post-synaptic activity [23]. For a given stimulation, LTD will occur if Δt > 0, while LTP will occur if Δt < 0. STDP is defined as the change in synaptic weight of the Δt between pre- and post-synaptic activity. By utilizing the waveforms adopted in Fig. 6a, b, the STDP curves for the amorphous HfO2 NVFET-based synapse are extracted with 100 ns spikes and shown in Fig. 6c. The pre-and the post-spike resembling the output of the leaky integrate-and-fire neurons are constitutive of an initial negative pulse followed by a sequence of positive pulses with the decreased amplitude. As shown in Fig. 6c, the amorphous HfO2 NVFET can stimulate the STDP learning rule successively with spiking period time TSTDP varying from 170 to 210 ns. The HfO2 NVFET obtains a steeper conductivity change around Δt = 0 at the TSTDP = 190 ns compared to the other TSTDP conditions, which is possibly due to the better matching between the spike waveform shape applied at the gate electrode and the non-volatile characteristics induced by ferroelectric-like behavior of the device.

Fig. 6
figure 6

a and b Spike timing waveform for the implementation of STDP. c Measured STDP curves in the amorphous HfO2 synaptic transistor with different spike periods (T = 170, 190, and 210 ns)

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Conclusions

In this work, we report an ultrathin amorphous HfO2 NVFET to emulate the bio-synapse. An MW of 0.56 V with an endurance above 106 cycles is experimentally demonstrated under the ± 3 V and 100 ns W/E pulses. Furthermore, various synaptic behaviors including STP under different stimuli, transitioning from STM to LTM, PPF, PTP, and STDP performance are realized in the device.