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Effects of Random Nanosized TiN Grain on Characteristic of Gate-All-Around FinFETs with Ferroelectric HZO Layer

Abstract

In this paper, we computationally study electrical characteristics for gate-all-around fin field effect transistors (GAA FinFETs) and negative capacitance GAA FinFETs (NC-GAA FinFETs) for sub-3-nm technological nodes. For the devices with the fin height of 55 nm, the on-state current increases (about 33% improvement) and the off-state current decreases (about 73% suppression) due to the NC effect. NC-GAA FinFETs have larger standard deviation of threshold voltage induced by the workfunction fluctuation (WKF) for both N-/P-type devices than those of GAA FinFETs. It is attributed to the variation of polarization in the different position of the ferroelectric layer. Notably, the inverter of NC-GAA FinFETs has larger noise margin and shorter delay time, compared with the inverter of GAA FinFETs; however, the characteristics of inverter of NC-GAA FinFETs suffer larger variability induced by the WKF.

Introduction

In order to develop low-power and high-performance electronic devices, the conventional way is to reduce the gate length of semiconductor devices. However, the technique of scaling down has caused the serious short-channel effect (SCE); and, the high leakage current was generated. The gate cannot control the channel effectively; therefore, fin-type field-effect transistors (FinFETs) have been proposed to substitute for planar MOSFETs. The contact area between gate and channel of FinFETs can be enlarged, so the channel controllability can be improved. Hence, FinFETs have been advanced in the current fabrication [1,2,3]. FinFETs have two different structures, bulk and silicon-on-insulator (SOI) FinFETs, respectively. SOI FinFETs have a buried oxide layer which can be used to reduce parasitic capacitance and improve characteristics but have a worse ability of heat dissipation. After the 1st generation FinFETs, to accommodate more transistors in the integrated circuits, it is necessary to reduce the fin pitch and increase the fin perimeter so that a higher total current can be obtained proportionally. Thus, 2nd and 3rd generation FinFETs have been studied [4, 5]. Intel claims that the fin height of 3rd generation FinFETs is 53 nm and the fin pitch is 34 nm in 10-nm fabrication. Semiconductor devices with the tall fin height will generate the higher current which may become the future trend of technology in the fabrication; however, the FinFET scaling still meets serious electrostatic problems and challenges. It will lead electrical characteristics to deteriorate.

To break through the bottleneck, the gate-all-around (GAA) structure where the channel is wrapped by the insulated oxide and metal gate layers has been a good candidate which can reduce the supply voltage, sustain the gate drive capability, and promise a high performance [6]. Recent results showed that characteristics of GAA structure could be enhanced sufficiently [7, 8]. Moreover, device characteristics are influenced by the different random effects in manufacturing processes. The effect of fluctuation sources for devices is always a key issue which should be considered. Researches have focused on several kinds of fluctuation sources; such as the random interface trap [9], random dopant fluctuation [10, 11], metal gate workfunction fluctuation (WKF) [12], and others. Among these fluctuation sources, the WKF is one of the crucial factors when the process of high-κ metal gate is adopted to enhance the device performance [13]. The concept of WKF is that the random distribution of the workfunction (WK) on the metal gate because the crystal orientation is unstable during the fabrication. Additionally, to achieve better electrical characteristics, the ferroelectric (FE) material has attracted the enormous attention in recent years [14, 15]. Getting deeper insight into the material physics, the FE material has the spontaneously polarized behavior and the symmetric two stable free energy valley in the energy distributed profile can be observed. The two stable spontaneous polarization states are defined as the two degenerate energy minima. By differentiating free energy with respect to the polarization for each position in the distributed profile, we can obtain the negative capacitance (NC) region from the result of polarization versus electric field [16]. The polarized FE layer exists the NC effect; thus, based on the concept of the FE polarization effect [17, 18], the dipoles in the FE layer will be switched as applying the external bias. It will improve the high leakage current and increase the on-state current (Ion) simultaneously [19, 20] and will further promise to boost the amplification gain and perform better characteristics. In order to obtain the obvious NC effect, the material of HfZrOx (HZO) successfully attracts the wide attention [21, 22]. Thus, NC field-effect transistors (NCFETs) have been considered to suppress the SCE; for example, the sub-threshold swing (SS) of NCFETs is below 60 mV/decade which will break the Boltzmann limitation in the conventional planar MOSFETs [23]. Unfortunately, the studies on GAA FinFETs with the FE stack have not been investigated yet.

In this study, we explore FinFETs with a GAA structure for sub-3-nm technological nodes to boost device characteristics. As the fin height is increased, Ion is enhanced, while the off-state current (Ioff) becomes worse. Thus, we further adopt a FE stack in the dielectric layer to alleviate the SCE effectively; we investigate the effect of WKF for both N-/P-type devices and its implication in inverter. This paper is organized as follows. In “Methods” section, the device configuration and simulation techniques are described in detail. In “Results and Discussion” section, the achieved results and their physical findings are discussed. Finally, we conclude this work and suggest future studies.

Methods

Computational Devices

Based on the aforementioned devices, many researches have demonstrated the comparison between bulk and SOI FinFETs [24]. To ensure the accuracy of the following simulation, we first calibrate the IDVG curve with experimental data [25], as shown in Fig. 1. The calibrated silicon (Si) nanosheet device is with the gate length of 12 nm, the nanosheet thickness of 5 nm, the nanosheet width of 25 nm, the effective oxide thickness of 0.66 nm, the spacing between the channels of 10 nm, and both S and D extensions of 5 nm. The workfunction of titanium nitride (TiN), the interface trap density and the lattice temperature are tuned [26] to align the measurement.

Fig. 1
figure 1

The calibrated IDVG curve between the simulation (black line) and the measurement (red symbol) of the N-type nanosheet MOSFET with gate length of 12 nm at VD of 0.7 V

Figure 2 shows the schematic plots of the three Si-based structures and the corresponding IDVG characteristics at VD = 0.7 V. The doping concentrations of S/D regions and channel are set as 1020 and 5 × 1017 cm−3, respectively. To prevent the leakage current from the S to D in the substrate, high doping concentrations (1019 cm−3) of boron and arsenic are adopted for N-/P-type FETs. As shown in Fig. 2b, the GAA FinFET has the largest Ion and the smallest Ioff among these devices. Table 1 lists the extracted SCE parameters for the three devices with similar values of the threshold voltage (Vth). A three dimensional (3D) schematic plot of the GAA FinFET is shown in Fig. 2c. Due to the insulated oxide and gate layers wrapping the channel, the gate can be controlled entirely; thus, devices will perform superiorly. Figure 2d, e shows cross sections of the 3D structure along different directions. In order to reduce the source/drain (S/D) resistance, the metal sidewall [26] is employed to increase Ion, as shown in Fig. 2e. The inter layer dielectric (ILD) is SiO2 and the metal gate is TiN in Fig. 2e. Table 2 lists the adopted device parameters, where the gate length (Lg) is 12 nm, the width (W) is 5 nm, and both source and drain extensions (Ls and Ld) are fixed at 5 nm. The effective oxide thicknesses (EOT) of the device with the FE layer (w/the FE) is 0.9 nm and that of the device without the FE layer (w/o the FE) is 0.7 nm, respectively. In addition, we compare devices for the three different fin heights (H), i.e., 55, 70 and 85 nm, respectively. To compare the devices w/and w/o the FEs accurately, we align the similar value of Vth for all devices (Vth = 240 mV). A 3D quantum-mechanically corrected device simulation is intensively performed to assess electrical characteristics. For NC-GAA FinFETs, the material of HZO is used as the FE layer because of an easier process for HZO compared with that of the PZT [27]. The Landau–Khalatnikov (LK) equation, E = 2αP + 4βP3 + 6γP5, is solved for the FE layer [28]. The adopted HZO parameters are listed in Table 3, where E is the electric field, P is the polarization, α, β and γ are FE parameters which have been calibrated with the experimental data [29]. Moreover, the simulation technique of WKF mainly follows our recent work in [30]. The cuboid method can provide a robust way to predict and analyze the degree of variability accurately compared with the Voronoi method. To analyze the effect of WKF on the device characteristics, 500 devices are randomly generated by considering probabilities of 60% and 40% for the distribution of high work function fluctuation (HWKF) and low work function fluctuation (LWKF) due to the metal grain of TiN 〈200〉 and TiN 〈111〉, respectively [31, 32].

Fig. 2
figure 2

a The schematic plots of GAA, bulk and SOI FinFETs, respectively. b The IDVG comparison among the three structures at VD = 0.7 V. c A 3D schematic of the GAA FinFET. A cross section of the 3D structure d in the x–y plane and e in the z–y plane

Table 1 Summary of electrical characteristics for GAA, bulk and SOI FinFETs, where they have the similar fin height of 20 nm, fin width of 17 nm, gate length of 22 nm, and EOT of 0.9 nm
Table 2 The adopted device parameters of N-/P-type GAA and NC-GAA FinFETs, where the fin heights are 55, 70 and 85 nm
Table 3 The adopted HZO parameters which have been calibrated with the measured data [28]

Settings of Workfunction Fluctuation

Figure 3a shows the schematic plot of the device with the fin height of 70 nm and a random WK distribution. Because of the variation of crystal orientation in the fabrication, the metal gate has different WK distributions. The WK of HWKF and LWKF for comparative devices is listed in Table 4. Both N-/P-type GAA FinFETs are set as the different WK and compared with NC devices in the statistical device simulation. In Fig. 3b, the different metal grain numbers (MGNs): 84, 102 and 120 which are corresponding to the fin heights: 55, 70 and 85 nm are shown. Notably, the white grain color is represented as HWKF and the green grain color is denoted as LWKF. Figure 3c, d shows the number of cases versus the number of HWKF for GAA and NC-GAA FinFETs under the fixed MGNs, where MGNs = (Lg/G) × (Weff/G), G is the average grain size, and Weff is the effective width of the metal gate. The randomly generated devices with a value of WK follows the Gaussian distribution.

Fig. 3
figure 3

a The schematic plot of the device with the fin height of 70 nm which has the WK random distribution. b The illustrations of random generation devices with the different MGNs. Notably, the white grain color is represented as HWKF; the green grain color is denoted as LWKF. The Gaussian distributions with HWKF for c GAA and d NC-GAA FinFETs under the fixed MGNs

Table 4 The WK of HWKF and LWKF for comparative devices

Results and Discussion

Figure 4a, b shows the IDVG characteristics of N-/P-type GAA and NC-GAA FinFETs with the different fin heights at VD = 0.7 V. To avoid the effect of FE hysteresis [33], a thin HZO film of 2.1 nm is adopted in this simulation. We find that the IDVG curves of NC-GAA FinFETs exhibit steeper SS than that of GAA FinFETs in Fig. 4c, d. Figure 4e reveals the Vth for both N-/P-type devices. We extract Vth by using the constant current method: (Weff/Lg) × 10–8 A. The values of Vth are similar by adjusting the value of WK under each fin height to obtain the physically reasonable comparison.

Fig. 4
figure 4

The IDVG characteristic of N-/P-type a GAA and b NC-GAA FinFETs with the different fin heights at VD = 0.7 V. The curves of NC-GAA FinFETs have no hysteresis and exhibit steeper SS than that of GAA FinFETs for c N-/, d P-type devices. e The Vth of GAA and NC-GAA FinFETs for N-/P-type devices. To obtain the precise device simulation results, we align the similar Vth for each device under the different fin heights conditions

Figure 5a, b compares the Ion for N-/P-type GAA and NC-GAA FinFETs. As the fin height increases, the Ion is enhanced because more induced charges are generated in the channel. With the fin height of 55 nm, NC-GAA FinFETs boost Ion of 32.8% for N-type and Ion of 48.0% for P-type devices compared with GAA FinFETs due to the NC effect of the FE layer. To offer a deeper insight into the mechanism of Ion, as shown in Fig. 5c, d, the current density in the zy plane for GAA and NC-GAA FinFETs with fin heights of 55 and 85 nm for both N-/P-type devices are demonstrated, which indicates that NC-GAA FinFETs can boost the current. Under the same fin height, the current density in the device w/the FE is significantly larger than that of the device w/o the FE. However, as shown in Fig. 6a, b, Ioff in the device w/o the FE is increased obviously when the channel height is increased. By considering the FE layer, 73.1%- and 72.8%-reduction in Ioff can be achieved for N-/P-type devices with the fin height of 55 nm, respectively. As shown in Fig. 6c, the conduction band energy from D to S (blue dashed line) will be extracted for all N-type devices. The off-state band diagrams of N-type GAA and NC-GAA FinFETs with the fin heights of 55 and 85 nm are demonstrated in Fig. 6d, e. The off-state band diagram of the NC-GAA FinFET shows a higher barrier than that of the GAA FinFET; thus, it can decrease the leakage current significantly. With the fin height of 55 nm, the off-state conduction band energy of the GAA FinFET is 283.6 meV and that of the NC-GAA FinFET is 319.7 meV which are based on the same measured point at S in the zoom-in plot of Fig. 6d; in Fig. 6e, with the fin height of 85 nm, the off-state conduction band energy of GAA FinFETs is 279.1 meV and that of NC-GAA FinFETs is 318.2 meV. The difference of off-state conduction band energy between the.

Fig. 5
figure 5

The comparison of Ion for a N-/, b P-type GAA/NC-GAA FinFETs. Because the metal sidewall can reduce the S/D resistance, the Ion is increased as the fin height increases. The current density of c N-/, d P-type GAA and NC-GAA FinFETs at the fin heights of 55 and 85 nm, respectively

Fig. 6
figure 6

The comparison of Ioff for a N-/, b P-type GAA and NC-GAA FinFETs. As the fin height increases, Ioff of GAA FinFETs is enhanced. NC-GAA FinFETs improve Ioff significantly. c The schematic plot of N-type devices which extracts the conduction band energy from D to S as the blue-dashed line. The off-state band diagram of N-type GAA and NC-GAA FinFETs with the fin heights of d 55 and e 85 nm. Compared with the GAA FinFET, the off-state band diagram of the NC-GAA FinFET shows the higher energy barrier than that of the GAA FinFET

GAA and NC-GAA FinFETs with respect to the fin height of 55 and 85 nm are 36.1 and 39.1 meV, respectively. It illustrates that the variation will achieve 8.3% (((39.1 meV − 36.1 meV)/36.1 meV) × 100%) when the fin height increases from 55 to 85 nm.

Figure 7a demonstrates a comparison of SS for GAA and NC-GAA FinFETs with different fin heights for N-/P-type devices. The results indicate that the polarized FE layer allows SS below to 60 mV/decade. Besides, we explore the behavior of circuit applications. In order to investigate the dynamic performance of inverter for GAA and NC-GAA FinFETs, the total capacitances (Cg) of N-/P- type GAA and NC-GAA FinFETs with the different fin heights are firstly shown in Fig. 7b, c. Because the channel induced charges is enhanced, the increase of Cg is proportional to the fin height. A comparison of inverters for devices w/and w/o the FE layer is revealed in Fig. 7d, where the delay time (τP) \(\propto {C}_{\mathrm{g}}\times {V}_{\mathrm{dd}}/{I}_{\mathrm{on}}\), and the Ion variation is larger than the Cg variation for both N-/P-type GAA and NC-GAA FinFETs (see Figs. 5a, b, 7b, c); thus, Ion dominates the dynamic performance of the inverter. As the fin height increases, the τP variation decreases ~ 10.09% for GAA FinFETs and ~ 9.92% for NC-GAA FinFETs.

Fig. 7
figure 7

a A comparison of SS for N-/P-type GAA and NC-GAA FinFETs. The FE layer has the strong NC effect which causes SS lower than 60 mV/decade. A comparison of Cg for b N-/, c P-type GAA and NC-GAA FinFETs. Cg is increased as the fin height increases. d τP of GAA and NC-GAA FinFETs. τP of NC-GAA FinFETs is lower than that of GAA FinFETs in each fin height condition

Figure 8a–c demonstrates the WKF with random 500 devices for the different MGNs. Notably, the dotted lines in each figure are denoted as nominal cases. For the cases of MGN = 102 (which is corresponding to the 70-nm fin height), Ion and Ioff versus HWKF numbers are shown in Fig. 8d, e, respectively. Figure 8f reveals the standard deviation of Vth (σVth) versus the different grain numbers for both N-/P-type devices. It can be observed that the σVth of GAA FinFETs is smaller than that of NC-GAA FinFETs which indicates that NC-GAA FinFETs perform more sensitively induced by the WKF. The reason is attributed to the variation of FE polarization. Based on the concept of the FE polarization, the polarization occurs when an external bias is applied. The FE layer will suffer the different degree of the polarization in each position [16]; for example, for the nominal case of N-type NC-GAA FinFET, the polarization corresponding to close to D, the middle of channel and S are − 5.3 × 10−7, − 5.1 × 10−7 and − 5.5 × 10–7 C/cm2, respectively. Owing to the nonuniform distribution of polarization, the FE layer has significant variability induced by the WKF; thus, the effect of WKF will become seriously and σVth will increase. It implies the usage of FE layer cannot suppress the WKF.

Fig. 8
figure 8

The WKF with random 500 devices for MGNs are a 84, b 102 and c 120. The distribution profiles of d Ion and e Ioff versus HWKF numbers for N-/P-type GAA and NC-GAA FinFETs with the fixed MGN. f The comparison of σVth versus the different MGNs. It can be observed that the σVth of GAA FinFETs is smaller than that of NC-GAA FinFETs. It implies that NC-GAA FinFETs perform more sensitively induced by the WKF

Figure 9a shows a comparison of Vth distribution of random 500 fluctuated N-type GAA and NC-GAA FinFETs. We select some cases with the same HWKF number (HWKF number is 62), such as Case A, Case B and the nominal case (Vth = 240 mV) for GAA FinFETs; Case C, Case D and the nominal case for NC-GAA FinFETs. These cases have different Vth, where Vth of Case A is 252 mV, Case B is 223 mV, Case C is 259 mV, and Case D is 178 mV. The one dimensional (1D) conduction band energy profile and the zoom-in plot from D to S to demonstrate comparative curves of Case A, Case B, and the nominal case for GAA FinFETs are shown in Fig. 9b. Compared with the nominal case, Case A has a higher energy barrier, a stronger channel control ability, and a relatively larger Vth. The difference of energy barrier between these cases is 13.0 meV. Similarly, the Vth of Case B is smaller than that of the nominal case which decreases 34.4 meV. The comparison of 1D conduction band profile and the zoom-in plot of Case C, Case D and the nominal case for NC-GAA FinFETs are shown in Fig. 9c. The difference of energy barrier between Case C and the nominal case is 23.0 meV; for Case D and the nominal case, the difference of energy barrier is around 53.0 meV. The Vth distribution of 500 random fluctuated P-type GAA and NC-GAA FinFETs is shown in Fig. 9d; similarly, the variation of Vth for P-type NC-GAA FinFETs is larger than that of P-type GAA FinFETs.

Fig. 9
figure 9

a The comparison of Vth distribution profile of random 500 fluctuated devices. The 1D conduction band energy profiles which are corresponding to six cases for b GAA and c NC-GAA FinFETs. d The relevant Vth distribution comparison profile of P-type devices

Figure 10a shows the Ion versus Ioff characteristic for N-type GAA and NC-GAA FinFETs with the same MGN. We select six cases for a further comparison. For GAA FinFETs, Case 1 and Case 2 have the same Ion but the different Ioff, where Ioff of Case 1 is larger than that of Case 2. One-dimensional conduction band profiles and zoom-in plots of Cases 1 and 2 are shown in Fig. 10b. The energy barrier of Case 1 is 80.0-meV reduction, compared with that of Case 2 (see zoom-in plots), which leads to a larger Ioff. Figure 10c reveals conduction band profiles and zoom-in plots of Cases 4 and 5 for NC-GAA FinFETs with different Ioff. From the zoom-in plots, the energy barrier of Case 5 is higher than that of Case 4 and the difference is 140.0 meV. Figure 10d shows the distribution of the current density of Cases 2 and 3 for GAA FinFETs. A larger current density can be observed in Case 2, compared with Case 3, which leads to a larger Ion. Similarly, a comparison of Cases 5 and 6 can also be investigated for NC-GAA FinFETs, as shown in Fig. 10e. Compared with GAA FinFETs for Cases 2 and 3, enhanced current densities of Cases 5 and 6 for NC-GAA FinFETs are observed obviously. Ion versus Ioff characteristic for P-type GAA and NC-GAA FinFETs with the same MGN is illustrated in Fig. 10f. The trend of the distribution is similar to N-type devices; the increased Ion and decreased Ioff can be obtained for NC-GAA FinFETs. Table 5 lists the standard deviation of Vth, Ion and Ioff for N-/P-type GAA and NC-GAA FinFETs under the same MGN; NC-GAA FinFETs have the larger variability of electrical characteristics than that of GAA FinFETs.

Fig. 10
figure 10

a The characteristic of IonIoff for N-type GAA and NC-GAA FinFETs with the same MGN. The 1D conduction band energy profiles and the zoom-in plots for b Cases 1 and 2 and c Cases 4 and 5 for GAA and NC-GAA FinFETs. The distribution of current density for d Cases 2 and 3 and e Cases 5 and 6 for GAA and NC-GAA FinFETs, respectively. f The characteristic of IonIoff for P-type GAA and NC-GAA FinFETs with the same MGN

Table 5 The standard deviation of Vth, Ion and Ioff for N-/P-type GAA and NC-GAA FinFETs under the same MGN (MGN = 102)

Figure 11a, b shows the distribution of Cg versus numbers of HWKF for N-/P-type GAA FinFETs; in addition, the distribution of Cg versus numbers of HWKF for N-/P-type NC-GAA FinFETs are revealed in Fig. 11c, d. The variation of the capacitance of NC-GAA FinFETs is larger than that of GAA FinFETs, which implies that NC-GAA FinFETs have a larger variability induced by the WKF. Without loss of generality, it demonstrates 7.5% for N-type and 6.3% for P-type NC-GAA FinFETs, and 6.0% for N-type and 5.2% for P-type GAA FinFETs which can confirm that NC-GAA FinFETs will suffer the severe effect of WKF in Cg. The comparison of capacitance difference (|Cg,high| − |Cg,low|) between N-type GAA and NC-GAA FinFETs is revealed in Fig. 11e. The capacitance differences of NC-GAA FinFETs are larger than those of GAA FinFETs with respect to different numbers of HWKF. For NC-GAA FinFETs with the number of HWKF of 60, when the device is with |Cg,high|, the values of polarization appearing at D, the middle of channel and S are − 6.3× 10−7, − 6.1 × 10−7 and − 7.2 × 10−7 C/cm2, respectively; additionally, when the device is with |Cg,low|, they are − 3.6 × 10−7, − 3.5 × 10−7 and − 3.9 × 10−7 C/cm2. It implies that the different degree of polarization in the FE layer will be obtained due to the nonuniform electric field; thus, the variation of surface potential of NC-GAA FinFETs will become large. The φs (which is define by |φs,D| − |φs,S|) comparison for N-type GAA and NC-GAA FinFETs is shown in Fig. 11f. The results indicate that NC-GAA FinFETs have higher φs compared with GAA FinFETs for different numbers of HWKF; thus, NC GAA-FinFETs are more sensitive when suffering from the WKF. Figure 11g shows the charge density distribution of N-type GAA and NC-GAA FinFETs for the number of HWKF of 60. The induced channel charges in the NC-GAA FinFETs is more than that of the GAA FinFETs, which results in a larger magnitude of Cg.

Fig. 11
figure 11

The comparison of Ion for a N-/, b P-type GAA/NC-GAA FinFETs. Because the metal sidewall can reduce the S/D resistance, Ion is increased as the fin height increases. The distributions of the current density of c N-/, d P-type GAA and NC-GAA FinFETs with the fin heights of 55 and 85 nm, respectively. e The comparison of capacitance difference (|Cg,high| −|Cg,low|) between N-type GAA/NC-GAA FinFETs under different HWKF numbers. f The surface potential (|φs,D| −|φs,S|) comparison of two devices under the different HWKF numbers. g The charge density distribution of two devices under the same HWKF number

Based on the achieved DC and AC characteristics of GAA and NC-GAA FinFETs, we do further explore the behavior of inverter constructed by these devices. Figure 12a shows the schematic plot of the inverter circuit which is composed of a P-type transistor and a N-type transistor. The voltage transfer curves of GAA and NC-GAA FinFETs considering WKF are demonstrated in Fig. 12b, c. Due to the effect of WKF, NC-GAA FinFETs have a larger σVIL and σVIH [34, 35] than that of GAA FinFETs; the fluctuation of noise margin low (σNML) of NC-GAA FinFETs is 12.0 mV and that of GAA FinFETs is 8.46 mV; the fluctuation of noise margin high (σNMH) of NC-GAA FinFETs is 10.9 mV and that of GAA FinFETs is 7.78 mV. The NM variation of NC-GAA FinFETs is with a 40%-increase compared with GAA FinFETs. Comparisons of NML and NMH for GAA and NC-GAA FinFETs with respect to different HWKF numbers are shown in Fig. 12d, e, respectively. Figure 12f shows the Vin and Vout versus time for GAA and NC-GAA FinFETs. The zoom-in plot which defines the characteristic of high-to-low delay time (tHL), low-to-high delay time (tLH), falling time (tf) and raising time (tr) are shown in Fig. 12g, h. Figure 12i shows comparisons of σtf, σtr and στp for GAA and NC-GAA FinFETs. Owing to different degrees of the FE polarization affected by the random position and number effects of WKF, the analyzed DC and AC characteristics including the results of Cg demonstrate that NC-GAA FinFETs have worse behavior than those of GAA FinFETs. Consequently, the performance including the NM and timing of the inverter with GAA FinFETs is superior to that of NC-GAA FinFETs.

Fig. 12
figure 12

a The schematic plot of the inverter circuit. The voltage transfer curve for b GAA and c NC-GAA FinFETs. The NML and NMH depend on VIL and VIH which are denoted in the plots. The comparison of NML and NMH for d GAA and e NC-GAA FinFETs. f The Vin and Vout versus time for two different devices. The zoom-in plots which define the characteristics of g tHL and tf and h tLH and tr for GAA FinEETs. i The comparison of σtf, σtr and στp for GAA and NC-GAA FinFETs

Conclusions

In summary, we have studied electrical characteristics of N-/P-type NC-GAA FinFETs for sub-3-nm technological nodes. The main findings of this work show that NC-GAA FinFETs have the better performance than that of GAA FinFETs. Compared with GAA FinFETs, more than 73% Ioff suppression and 33% Ion boost have been achieved. Besides, we have analyzed the effect of WKF for 500 random devices; we observed that the σVth of NC-GAA FinFETs is larger than that of GAA FinFETs, which increases the variability of N-type NC devices for 34% (((17.11 mV − 12.73 mV)/12.73 mV) × 100%) and P-type NC devices for 41% (((16.49 mV − 11.69 mV)/11.69 mV) × 100%). Based on the achieved DC and AC characteristics, the application of inverter with NC-GAA FinFETs has shown a worse performance including NM and timing than that of GAA FinFETs. The NM variation of NC-GAA FinFETs increases 40% compared with GAA FinFETs. This work has reported a comprehensive study for the emerging GAA FinFETs from the perspective of electrical and physical characteristics. It can benefit the device design and fabrication for sub-3-nm technological nodes.

Availability of data and materials

All data generated or analyzed during this study are included in this published article.

Abbreviations

Si:

Silicon

GAA:

Gate-all-around

FinFET:

Fin field effect transistor

NC:

Negative capacitance

WKF:

Workfunction fluctuation

SCE:

Short-channel effect

WK:

Workfunction

FE:

Ferroelectric

I on :

On-state current

HZO:

HfZrOx

NCFET:

NC field-effect transistors

SS:

Subthreshold swing

I off :

Off-state current

Si:

Silicon

TiN:

Titanium nitride

V th :

Threshold voltage

3D:

Three dimensional

S/D:

Source/drain

ILD:

Inter layer dielectric

L g :

Gate length

W :

Width

L s/L d :

Source and drain extensions

EOT:

The effective oxide thickness

H:

Fin heights

LK:

Landau–Khalatnikov

HWKF:

High work function fluctuation

LWKF:

Low work function fluctuation

MGN:

Metal grain number

G :

The average of grain size

W eff :

Metal gate effective width

C g :

The total capacitance

τP :

The delay time

σV th :

The standard deviation of Vth

σNML :

The standard deviation of noise margin low

t HL :

The high-to-low delay time

t LH :

The low-to-high delay time

t f :

The falling time

t r :

The raising time

References

  1. Li Y, Hwang C (2007) Effect of fin angle on electrical characteristics of nanoscale round-top-gate bulk FinFETs. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2007.908908

    Article  Google Scholar 

  2. Sasaki Y, Ritzenthaler R, Keersgieter AD et al (2015) A comparison of arsenic and phosphorus extension by room temperature and hot ion implantation for NMOS Si bulk-FinFET at N7 (7nm) technology relevant fin dimensions. Proc Symp VLSI Technol. https://doi.org/10.1109/VLSIT.2015.7223691

    Article  Google Scholar 

  3. Yang FL, Lee DH, Chang HY et al (2004) 5nm-gate nanowire FinFET. Proc Symp VLSI Technol. https://doi.org/10.1109/VLSIT.2004.1345476

    Article  Google Scholar 

  4. Wu SY, Lin CY, Chiang MC et al (2014) An enhanced 16 nm CMOS technology featuring 2nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications. IEDM Tech Dig. https://doi.org/10.1109/IEDM.2014.7046970

    Article  Google Scholar 

  5. Auth C, Aliyarukunju A, Asoro M et al (2017) A 10 nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, self-aligned quad patterning, contact over active gate and cobalt local interconnects. IEDM Tech Dig. https://doi.org/10.1109/IEDM.2017.8268472

    Article  Google Scholar 

  6. Song JY, Choi WY, Park JH, Lee JD, Park BG (2006) Design optimization of gate-all-around (GAA) MOSFETs. IEEE Trans Nanotechnol. https://doi.org/10.1109/TNANO.2006.869952

    Article  Google Scholar 

  7. Nagy D, Indalecio G, Garcia-Loureiro AJ et al (2018) FinFET versus gate-all-around nanowire FET: performance, scaling, and variability. IEEE J Electron Dev Soc. https://doi.org/10.1109/JEDS.2018.2804383

    Article  Google Scholar 

  8. Zheng P, Liao YB, Damrongplasit N, Chiang MH, Liu TJK (2014) Variation-aware comparative study of 10-nm GAA Versus FinFET 6-T SRAM performance and yield. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2014.2360351

    Article  Google Scholar 

  9. Hsu SC, Li Y (2014) Electrical characteristic fluctuation of 16-nm-gate high-κ/metal gate bulk FinFET devices in the presence of random interface traps. Nanoscale Res Lett. https://doi.org/10.1186/1556-276X-9-633

    Article  Google Scholar 

  10. Huang WT, Li Y (2015) Electrical characteristic fluctuation of 16-nm-gate trapezoidal bulk FinFET devices with fixed top-fin width induced by random discrete dopants. Nanoscale Res Lett. https://doi.org/10.1186/s11671-015-0739-0

    Article  Google Scholar 

  11. Sung WL, Chang HT, Chen CY, Chao PJ, Li Y (2016) Statistical device simulation of characteristic fluctuation of 10-nm gate-all-around silicon nanowire MOSFETs induced by various discrete random dopants. In: Proceedings of IEEE 16th international conference on nanotechnology. https://doi.org/10.1109/NANO.2016.7751556

  12. Lee Y, Shin C (2017) Impact of equivalent oxide thickness on threshold voltage variation induced by work-function variation in multigate devices. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2017.2673859

    Article  Google Scholar 

  13. Takeuchi H, Wong HY, Ha D, King TJ (2004) Impact of oxygen vacancies on high-κ gate stack engineering. IEDM Tech Dig. https://doi.org/10.1109/IEDM.2004.1419305

    Article  Google Scholar 

  14. Cao W, Banerjee K (2020) Is negative capacitance FET a steep-slope logic switch? Nat Commun. https://doi.org/10.1038/s41467-019-13797-9

    Article  Google Scholar 

  15. Li KS, Chen PG, Lai TY et al (2015) Sub-60mV-swing negative-capacitance FinFET without hysteresis. In: IEEE international electron devices meeting. https://doi.org/10.1109/IEDM.2015.7409760

  16. Hoffmann M, Fengler FPG, Herzig M et al (2019) Unveiling the double-well energy landscape in a ferroelectric layer. Nature. https://doi.org/10.1038/s41586-018-0854-z

    Article  Google Scholar 

  17. Hoffmann M, Mikolajick T (2020) Experimental ferroelectric energy landscapes: insights into the origin of negative capacitance. In: Joint conference of the IEEE international frequency control symposium and international symposium on applications of ferroelectrics. https://doi.org/10.1109/IFCS-ISAF41089.2020.9234897

  18. Saha AK, Sharma P, Dabo I, Datta S, Gupta SK (2017) Ferroelectric transistor model based on self-consistent solution of 2D Poisson's, non-equilibrium Green's function and multi-domain Landau Khalatnikov equations. In: IEEE international electron devices meeting. https://doi.org/10.1109/IEDM.2017.8268385

  19. Kwon D, Cheema S, Shanker N et al (2019) Negative capacitance FET with 1.8-nm thick Zr-doped HfO2 oxide. IEEE Electron Dev Lett. https://doi.org/10.1109/LED.2019.2912413

    Article  Google Scholar 

  20. Ko E, Lee H, Goh Y, Jeon S, Shin C (2017) Sub-60-mV/decade negative capacitance FinFET With Sub-10-nm hafnium-based ferroelectric capacitor. IEEE J Electron Dev Soc. https://doi.org/10.1109/JEDS.2017.2731401

    Article  Google Scholar 

  21. Lee MH, Chen PG, Liu C et al (2015) Prospects for ferroelectric HfZrOx FETs with experimentally CET = 0.98 nm, SSfor = 42 mV/dec, SSrev = 28 mV/dec, switch-OFF < 0.2V, and hysteresis-free strategies. In: IEEE international electron devices meeting. https://doi.org/10.1109/IEDM.2015.7409759

  22. Li J, Zhou J, Han G et al (2017) Correlation of gate capacitance with drive current and transconductance in negative capacitance Ge PFETs. IEEE Electron Dev Lett. https://doi.org/10.1109/LED.2017.2746088

    Article  Google Scholar 

  23. Yeung CW, Khan AI, Salahuddin S, Hu C (2013) Device design considerations for ultra-thin body non-hysteretic negative capacitance FETs. In: Third Berkeley symposium on energy efficient electronic systems. https://doi.org/10.1109/E3S.2013.6705876

  24. Brown AR, Konstantin ND, Bourdelle KK, Nguyen BY, Asenov A (2013) Comparative simulation analysis of process-induced variability in nanoscale SOI and bulk trigate FinFETs. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2013.2281474

    Article  Google Scholar 

  25. Loubet N, Hook T, Montanini P et al (2017) Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In: Proceedings of symposium on VLSI technology. https://doi.org/10.23919/VLSIT.2017.7998183

  26. Sung WL, Li Y (2021) Characteristics of stacked gate-all-around Si nanosheet MOSFETs with metal sidewall source/drain and their impacts on CMOS circuit properties. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2021.3074126

    Article  Google Scholar 

  27. Kim SJ, Mohan J, Summerfelt SR, Kim J (2019) Ferroelectric Hf0.5Zr0.5O2 thin films: a review of recent advances. JOM. https://doi.org/10.1007/S11837-018-3140-5

    Article  Google Scholar 

  28. Pahwa G, Dutta T, Agarwal A, Chauhan YS (2017) Compact model for ferroelectric negative capacitance transistor with MFIS structure. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2017.2654066

    Article  Google Scholar 

  29. Kao MY, Sachid AB, Lin YK et al (2018) Variation caused by spatial distribution of dielectric and ferroelectric grains in a negative capacitance field-effect transistor. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2018.2864971

    Article  Google Scholar 

  30. Sung WL, Yang YS, Li Y (2021) Work-function fluctuation of gate-all-around silicon nanowire n-MOSFETs: a unified comparison between cuboid and voronoi methods. IEEE J Electron Dev Soc. https://doi.org/10.1109/JEDS.2020.3046608

    Article  Google Scholar 

  31. Dadgour H, Endo K, De V, Banerjee K (2008) Modeling and analysis of grain orientation effects in emerging metal-gate devices and implications for SRAM reliability. In: IEEE international electron devices meeting. https://doi.org/10.1109/IEDM.2008.4796792

  32. Dadgour H, De V, Banerjee K (2008) Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design. IEEE/ACM international conference on computer-aided design.https://doi.org/10.1109/ICCAD.2008.4681585

  33. Lin C, Khan AI, Salahuddin S, Hu C (2016) Effects of the variation of ferroelectric properties on negative capacitance FET characteristics. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2009.2022692

    Article  Google Scholar 

  34. Li Y, Hwang CH, Li TY (2009) Random-dopant-induced device variability in nano-CMOS and digital circuits. IEEE Trans Electron Dev. https://doi.org/10.1109/TED.2009.2022692

    Article  Google Scholar 

  35. Li Y, Hwang CH, Li TY (2009) Discrete-dopant-induced timing fluctuation and suppression in nanoscale CMOS circuit. IEEE Trans Circuits Syst II Express Briefs. https://doi.org/10.1109/TCSII.2009.2019168

    Article  Google Scholar 

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Acknowledgements

This work was supported in part by the Ministry of Science and Technology, Taiwan, under Grant MOST 110-2221-E-A49-139, Grant MOST 109-2221-E-009-033 and Grant MOST 109-2634-F-009-030 and in part by the Center for mm Wave Smart Radar Systems and Technologies under the Featured Areas Research Center Program within the framework of the Higher Education Sprout Project by the Ministry of Education in Taiwan.

Funding

Grant MOST 110-2221-E-A49-139, Grant MOST 109-2221-E-009-033 and Grant MOST 109-2634-F-009-030.

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YL: Supervision. YL, MHC, YCT: Performing the simulation, preparation, reviewing, editing of original draft, and approved the final manuscript. All authors read and approved the final manuscript.

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Correspondence to Yiming Li.

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Li, Y., Chuang, MH. & Tsai, YC. Effects of Random Nanosized TiN Grain on Characteristic of Gate-All-Around FinFETs with Ferroelectric HZO Layer. Nanoscale Res Lett 17, 16 (2022). https://doi.org/10.1186/s11671-022-03657-9

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Keywords

  • Short channel effect
  • Gate-all-around
  • FinFET
  • Negative capacitance
  • Ferroelectric
  • Work-function fluctuation
  • Nano-sized metal grain