Fig. 2From: Effects of Random Nanosized TiN Grain on Characteristic of Gate-All-Around FinFETs with Ferroelectric HZO Layera The schematic plots of GAA, bulk and SOI FinFETs, respectively. b The ID–VG comparison among the three structures at VD = 0.7 V. c A 3D schematic of the GAA FinFET. A cross section of the 3D structure d in the x–y plane and e in the z–y planeBack to article page