Skip to main content

Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory


Three-terminal (3-T) thyristor random-access memory is explored for a next-generation high-density nanoscale vertical cross-point array. The effects of standby voltages on the device are thoroughly investigated in terms of gate–cathode voltage (VGC,ST) and anode–cathode voltage (VAC,ST) in the standby state for superior data retention characteristics and low-power operation. The device with the optimized VGC,ST of − 0.4 V and VAC,ST of 0.6 V shows the continuous data retention capability without refresh operation with a low standby current of 1.14 pA. In addition, a memory array operation scheme of 3-T TRAM is proposed to address array disturbance issues. The presented array operation scheme can efficiently minimize program, erase and read disturbances on unselected cells by adjusting gate–cathode voltage. The standby voltage turns out to be beneficial to improve retention characteristics: over 10 s. With the proposed memory array operation, 3-T TRAM can provide excellent data retention characteristics and high-density memory configurations comparable with or surpass conventional dynamic random-access memory (DRAM) technology.


The scaling down of dynamic random-access memory (DRAM) cell has been continuously required for high-density, high-speed, and low-power operations [1,2,3] However, the conventional one transistor-one capacitor (1T- 1C) DRAM is facing an inevitable problem: it is increasingly difficult to achieve the required capacitance to differentiate the two states (~ 10 fF/cell) with the smaller cell area [4]. Even though there have been many studies to improve the capacitor technologies, such as new high-k materials [5,6,7] and a high-aspect-ratio 3D capacitor structure [8, 9], these approaches possess the issue of increasing fabrication complexities and high cost [2, 3]. To overcome these challenges, a capacitorless 1T DRAM structure, namely a thyristor-based random-access memory (TRAM), has been proposed as an alternative in which the charge is stored at the internal p-base and n-base storage area [10,11,12,13,14,15,16]. The TRAM can operate as a two-terminal (2-T) device by modulating the energy band with only the anode and cathode biases [10,11,12]. 2-T TRAM has the advantage of its simple structure that allows a cost-effective cross-point array fabrication with conventional Si processes. Yet, the drawbacks are the low data retention and array disturbance that stem from the weak controllability and asymmetric of the storage areas [10,11,12]. The 2-T TRAM has a limit to overcome these drawbacks by controlling the two storage areas with only anode–cathode bias because electrons and holes exhibit a difference in mobility and lifetime. On the other hand, a three-terminal (3-T) TRAM, whose gate bias controls the energy band of the storage region, can remedy these drawbacks; the proper adjustment of gate–cathode voltage (VGC) can improve the retention characteristics and the array disturbance immunity by anode–cathode voltage (VAC) [13,14,15,16]. But an array operating conditions using the standby voltages for continuous retention characteristics and high disturbance immunity have not been reported yet. In terms of cell density, if a vertical channel transistor (VCT) is adopted, 4F2 memory feature size can be achievable with the 3-T TRAM [17, 18].

This paper aims at providing memory operating voltage guidelines with optimized standby voltages in the 3-T TRAM array configurations. The effects of the gate–cathode voltage on the standby state (VGC,ST) are thoroughly investigated for low-power operations and better retention characteristics. To maintain the stored charges in the storage area with the lowest standby current, a minimum anode–cathode voltage on the standby state (VAC,ST) is obtained from the anode current–anode voltage characteristics (IA-VAC). Furthermore, for a reliable array operation, the operating conditions are suggested to avoid any possible array disturbance using the optimal standby voltage.

Simulation Methods

Figure 1 shows a schematic diagram of a 3-T TRAM unit cell and a possible cross-point vertical array configuration. The 3-T TRAM consists of physical p+-anode—n-base—p-base—n+-cathode layers with a gated p-base. The anode and cathode areas are highly doped with a doping concentration of 1 × 1020 cm−3, and the base areas (p- and n-base) have the same Gaussian doping profile with a peak value of 1.6 × 1018 cm−3, which have similar doping concentrations in real device. This symmetric doping profile can secure memory hysteresis characteristics and sufficient memory window margin. If the lengths of both n- and p-bases are shorter than the sum of the depletion width inside the storage areas, sensing margin and storage capacity are reduced. On the other hand, when the length of both bases is longer than the sum of the depletion width, the robustness of the memory structure is worsened due to the high vertical aspect ratio of the 3-T TRAM. Therefore, the lengths of both n- and p-bases are set to 100 nm considering the junctions' depletion widths [12]. The channel area is 20 × 20 nm2, and the thickness of the gate oxide is 5 nm. The gate and cathode electrodes are designed as a word line (WL) and a bit line (BL), respectively.

Fig. 1
figure 1

Schematic diagrams of a 3-T TRAM unit cell and b cross-point vertical 3-T TRAM array

Si-based 3-T TRAM cells are simulated using Sentaurus technology computer-aided design (TCAD) [19]. To reliably simulate the Si-based 3-T TRAM, the physics models of the simulation are adjusted by using the experimental data of IAVAC characteristics for various VGCs in the Si-based thyristor memory device with a gated base (Fig. 2) [20]. Specifically, the parameters of the recombination model are adjusted and the Si-SiO2 surface SRH recombination model is adopted to reflect the data retention characteristics of real devices affected by junction and interface defects. Usual drift–diffusion transport model with Fermi–Dirac distribution is used. Philips unified mobility model is adopted to consider the carrier-impurity and carrier-carrier scatterings [21], and the high-field saturation and doping-dependent mobility models are also used. Oldslotboom bandgap narrowing model [22] is used to consider the highly doped silicon regions. Doping-dependent Shockley–Read–Hall (SRH) [23] and Auger recombination [24] models are adopted to account for the carrier recombination at the junctions. The avalanche generation [25] and band-to-band tunneling [26] models are also considered to calculate the carrier generations and the tunneling. The pulses applied to all memory operations have the rise time (Trise) and the fall time (Tfall) of 0.25 ns, while the hold time (Thold) is 2 ns [12]. The operation speed inferred from these pulse parameters is comparable to the modern DRAM memory clock rate [27].

Fig. 2
figure 2

IA-VAC characteristics for various VGCs simulation results (lines) adjusted to the experimental data (symbols) of the p+npn+ silicon memory device with a gated base

Results and Discussion

Optimization of Standby Voltages

Figure 3a shows two possible approaches to program a cell. In both approaches, the cathode voltage (VC) is defined as 0.0 V. However, the voltage differences between the gate and the cathode in the standby state (VGC,ST) are set to two different values. − 0.4 V (right) is the optimized value, while 0.0 V (left) is the conventional case for a comparison. The device with the VGC,ST of − 0.4 V has a low program anode–cathode voltage (VAC,P) of 1.2 V, and this is only a half of VAC,P required when VGC,ST is 0.0 V. This low VAC,P is attributed to the accumulated holes in p-base by the negative VGC,ST. When the VGC rapidly rises to 0.4 V for a program operation, the accumulated holes by the negative VGC,ST (− 0.4 V) reduce the energy band barrier height in the p-base (HP). As such, the device with the optimized VGC,ST minimizes the power consumption in program operation since a smaller VAC,P is required to reduce the HP. Figure 3b shows the stored hole density in the p-base (NP) as a function of standby time at state-1 (TST,1) after the program pulse. As the TST,1 increases, the NP decreases due to the carrier recombinations at the junctions. Due to the low VAC,P, the device with VGC,ST of − 0.4 V exhibits lower NP than the case of 0.0 V in the early stage (TST,1 < 10 μs). However, the NP in the later stage (TST,1 > 10 s) is higher than the case of 0.0 V. This higher NP is the result of the low recombination rate caused by the depletion of electrons in the p-base due to the negative VGC,ST. Figure 3c shows the energy band diagrams of 3-T TRAM at 10 ms after a program pulse to investigate the data retention characteristic depending on VGC,ST. The left side is for VGC,ST = 0.0 V, and the right side is for VGC,ST = − 0.4 V. The HP difference between the state-0 and state-1 at 10 ms after a program pulse exhibits a high value of 0.17 eV with the optimized VGC,ST of − 0.4 V due to the long-lasting NP. This indicates that the device with an optimized VGC,ST has an improved data retention characteristics that can maintain the low-resistance state (state-1) for a longer time.

Fig. 3
figure 3

a Program operation conditions at a VC of 0 V when a VGC,ST is 0.0 V (left) and − 0.4 V (right). b NP as a function of TST,1 at different VGC,ST of 0.0 V (black line) and − 0.4 V (red line). c Energy band diagrams at 10 ms of TST,1 when VGC,ST is 0.0 V (left) and − 0.4 V (right)

Figure 4a shows IAVAC characteristics for the VAC pulse with Trise of 1000 s, Thold of 2 ns and Tfall of 1000 s when VGC is fixed at − 0.4 V. It has been previously reported that the IAVAC curve with long Tfall of 1000 s can effectively provide a minimum VAC,ST to improve the data retention characteristics [12]. When VGC is fixed to − 0.4 V, the device exhibits a rapid increase of IA at VAC = 2.65 V representing a switching from the state-0 to the state-1. This indicates that a higher VAC is required to switch the state as long as VGC is maintained below − 0.4 V, and thus the state is well protected. As mentioned above, for a normal programming, only 1.2 V of VAC,P is required since VGC is increased from − 0.4 to 0.4 V. As such, for VAC,P less than 2.6 V applied to the bit line (BL) in array operation, 3-T TRAM can avoid unwanted program errors if the voltage of the word line (WL) is fixed to VGC,ST = − 0.4 V or below.

Fig. 4
figure 4

a IAVAC characteristics of the 3-T TRAM by the VAC pulse with Trise, Tfall = 1000 s, Thold = 2 ns when the VGC is fixed at − 0.4 V. b NP as a function of TST,1 at different VAC,ST of 0.5 V (black line) and 0.6 V (red line). c Energy band diagrams at TST,1 = 10 s with different VAC,ST of 0.5 V and 0.6 V

In the downward VAC sweep (Tfall), the switching of the state occurs at 0.56 V as evidenced by the sharp slope (red dashed line in Fig. 4a). Thus, the state-1 can be maintained at VAC,ST of 0.56 V. To investigate this drastic change by the voltage difference as small as 0.1 V, NP as a function of TST,1 is examined for two different VAC,ST of 0.5 V and 0.6 V (Fig. 4b). For VAC,ST = 0.5 V, the stored holes disappear rapidly after 10 μs, but for VAC,ST = 0.6 V, the device can maintain a high NP of about 1.47 × 1018 cm−3 for more than 10 s which is 106 times larger. Figure 4c shows the energy band diagrams of 3-T TRAM at TST,1 = 10 s for two different VAC,ST of 0.5 V and 0.6 V. With VAC,ST of 0.6 V, holes more than the amount recombines are injected into the base region, and the state-1 band shape along with the stored charge are maintained. With VAC,ST of 0.5 V, on the other hand, the holes injection is not enough to compensate the loss of holes by recombination, and the stored charge rapidly disappears, returning the band shape back to that of the state-0. A device with VAC,ST lower than 0.5 V will face similar level or faster charge loss. Considering the clock speed of modern VLSI circuit, the 3-T TRAM with VAC.ST of 0.6 V can exhibit the continuous state-1 virtually without a refresh operation. In addition, despite the high VAC,ST of 0.6 V, the device has a standby current as low as 1.14 pA, suggesting that the 3-T TRAM with the VAC,ST of 0.6 V is suitable for a low-power operation.

Memory Operation of 3-T TRAM Array

Compared to the 2-T TRAM without the gate terminal, the 3-T TRAM has a strong state immunity against the change of anode–cathode potential by controlling the storage potential with the gate terminal. On the other hand, the shift in gate–cathode potential in the 3-T TRAM easily interferes with the stored information. This disturbance is studied by assuming an operation pulse applied to a nearby cell. The cell under the study is initially at unselected bias condition, and the subject cell's states after the disturbance are observed. Figure 5 shows the schematic of a memory-cell-array configuration of 3-T TRAM. Our study shows that, with a proper operating scheme (maintaining fixed VGC to the unselected cells), this memory-cell-array configuration can prevent unselected cells' unwanted changes. For an efficient adjustment of VGC in the memory operation, the gate and cathode electrodes are set to the WL and BL, respectively. The anode electrode is fixed at 0.6 V. Table. 1 shows the operating voltage conditions for the 3-T TRAM array. To maintain the stable state-0 and state-1 in the standby state, VG and VC in the standby state are set to − 0.4 V and 0.0 V with the VA of 0.6 V. The operation strategies to prevent the array disturbance, found through our study, are summarized for each operation (program, erase and parallel read) as the followings.

Fig. 5
figure 5

Schematic diagram of the 3-T TRAM memory-cell-array configuration

Table 1 Operating voltage condition of 3-T TRAM array

Program: To program the selected cell, the selected VC decreases from 0.0 to − 0.8 V as shown in Table 1. This decreased VC can facilitate the influx of carriers into the base region. As such, the selected cell is programmed with the VGC of 0.4 V and VAC of 1.4 V. Figure 6a shows the simulated energy band diagrams of the cell under programming at TST,0 and TST,1 = 10 s. The selected cell for the program operation can maintain the state-1 with low HP even at the high TST,1 of 10 s. However, the problem with the above approach is that all cells in the selected BL experience unwanted program operation by the VGC of 0.4 V and VAC of 1.4 V, which are larger than the VGC of 0.4 V and VAC,P of 1.2 V, respectively. To prevent this unwanted programming, VG in all WLs except for the selected WL can be decreased from − 0.4 to − 1.2 V. In this way, the VGC can be recovered back to − 0.4 V from 0.4 V. Figure 6b shows the simulated energy band diagrams of the unselected cells at TST,0 and TST,1 = 0 s. The unselected cells exhibit no change in energy band with the VAC of 1.4 V if VGC is below − 0.4 V. Thus, the selected cell exhibits the continuous state-1, while the unselected cells can avoid the unwanted program disturbance.

Fig. 6
figure 6

Energy band diagrams of a the selected cell for programming at TST,0 (black line) and TST,1 = 10 s (red line) and b that of the unselected cells at TST,0 (black line) and TST,1 = 0 s (red line)

Erase: To erase a selected cell, the VG and VC of the selected WL and BL should be increased from − 0.4 to 0.8 V and 0.0 to 0.4 V, respectively, as shown in Table 1. In Fig. 7a, the NP is investigated as a function of TST,0 after the erase operation at TST,1 of 2.5 ns. The NP is decreased due to the depletion of stored holes in the p-base as the VGC increases from − 0.4 to 0.4 V. Also, the hole injection into the p-base during the erase operation is restrained by decreasing VAC from 0.6 to 0.2 V. As the TST,0 increases, the NP is back to 0 cm−3, which represents the complete state-0. To investigate the reason, the energy band diagram at TST,0 of 2.5 ns is examined and compares with the energy band at TST,1 of 2.5 ns (Fig. 7b). After the erase operation, the n-base (HN) energy band height decreases as the HP increases. The holes in the anode flow into the p-base over the lowered HN and the NP increase. The number of injected holes decreases due to the increased HN by the recombination process, so the NP saturates at 0 cm−3 as TST,0 increases. From this result, it is found that the cell selected for the erase operation can exhibit the state-0 with the sufficiently high HP at any TST,0. However, the erasing method with the increased VGC of the selected WL can cause a problem of erasing all cells on the same WL. To avoid this issue, the VGC should be reduced from 0.4 to − 0.4 V by increasing VC from 0.0 to 1.2 V on all BLs except for the selected BL (Table 1). Accordingly, the erase disturbance pulse with VAC = − 0.6 V and VGC = − 0.4 V applies to the unselected cells on the same WL. The state-1 should be detectable at any time even if this erase disturbance pulse is repeated after the NP is saturated to the lowest value of 1.47 × 1018 cm−3. To confirm this, as shown in Fig. 7c, the NP is examined as a function of the number of this erase disturbance pulse. Despite the repeated disturbance pulses, NP exhibits a negligible decrease near 1.1 × 1018 cm−3 so that the device can maintain the state-1. In addition, the slightly reduced NP can readily return to its original state-1 by applying read operation. Therefore, the 3-T TRAM can overcome the erase disturbance by controlling the VGC in unselected cells,

Fig. 7
figure 7

a NP as a function of TST,0 after the erase operation at TST,1 = 2.5 ns. b Energy band diagrams at TST,1 = 2.5 ns and TST,0 = 2.5 ns. c NP as a function of the number of the erase disturbance pulse

Parallel Read: To perform the parallel read operations on the cells that share the same BL, the VC of the selected BL and the VG of all WLs are set to − 0.8 V (Table 1). If the VC in the selected BL is decreased to − 0.8 V, not only VAC increases to 1.4 V but also VGC increases to 0.4 V. This high VGC lowers the HP and causes unwanted program errors of the cells in the selected BL. To avoid this, the VG in all WLs should be decreased to − 0.8 V so that 0.0 V of VGC and 1.4 V of VAC are applied to the cells in the selected BL. To investigate the effect of the read operation on the state-0, the operating voltage and anode current are extracted after ten consecutive read operations are applied following an erase operation as shown in Fig. 8a. Although the ten continuous read pulses are applied to the device after the erase operation, the read current gradually decreases, confirming that the state-0 stably is maintained. This result indicates that the 3-T TRAM with the suggested array configuration for reading exhibits a reliable disturbance immunity for the state-0. Additionally, to confirm the detectability of the state-1, the operating voltage and anode current for a program and a read with the TST,1 of 10 s are extracted (Fig. 8b). The read pulse can detect the state-1 continuously with a high current even at a long TST,1 of 10 s.

Fig. 8
figure 8

Operating voltage and anode current a when ten consecutive read operations are applied after the erase operation and b when a read operation is applied at TST,1 = 10 s


We have investigated the effects of the VGC,ST and VAC,ST of the nanoscaled 3-T TRAM for low-power operation and better retention characteristics. The optimized VGC,ST of − 0.4 V allows a lower VAC,P due to the accumulated holes in the standby state. In addition, a low HP remains for a longer time because the optimized VGC,ST effectively maintains the high NP by reducing carrier recombinations at the junctions. The investigation of IAVAC characteristics suggests that a minimum VAC,ST of 0.6 V enables the device to exhibit the continuous state-1 without refresh operation while allowing a small standby current of 1.14 pA. Furthermore, a memory array operation strategy with the proper VGC,ST and VAC,ST for the 3-T TRAM is presented for the first time to implement reliable array operations without refresh and disturbances. The adjustment of VGC can effectively minimize the program, erase and read disturbances in unselected cells. Along with the high immunity against array disturbances, the 3-T TRAM with the optimum strategy for array operations exhibits superior data retention capability than conventional 1T-1C DRAM technology. Thus, the proposed memory array operation scheme can provide a way to realize capacitorless 1T DRAM with 3-T TRAM.

Availability of data and materials

All data are fully available without restriction.



Dynamic random-access memory


One transistor-one capacitor




Thyristor-based random-access memory








Vertical channel transistor

V A :

Anode voltage

V G :

Gate voltage

V C :

Cathode voltage

V GC :

Gate–cathode voltage

V AC :

Anode–cathode voltage


VGC on the standby state


VAC on the standby state

I A :

Anode current


Word line


Bit line


Technology computer-aided design

T rise :

Rise time

T fall :

Fall time

T hold :

Hold time

V AC,P :

Program anode–cathode voltage

H P :

Energy band barrier height in the p-base

H N :

Energy band barrier height in the n-base

N P :

Stored hole density in the p-base

T ST,1 :

Standby time at state-1

T ST,0 :

Standby time at state-0


Very large-scale integration


  1. Kim SK, Lee SW, Han JH, Lee B, Han S, Hwang CS (2010) Capacitors with an equivalent oxide thickness of <0.5 nm for nanoscale electronic semiconductor memory. Adv Funct Mater 20(18):2989–3003

    Article  CAS  Google Scholar 

  2. Park SK (2015) Technology scaling challenge and future prospects of DRAM and NAND flash memory. In: Proceedings of the IEEE International Memory Workshop (IMW), pp 1–4

  3. Lee SH (2016) Technology scaling challenges and opportunities of memory devices. In: International Electron Devices Meeting. Technical Digest, pp 1–8

  4. Kim SK, Popovici M (2018) Future of dynamic random-access memory as main memory. MRS Bull 43(5):334–339

    Article  Google Scholar 

  5. Froehlich K, Aarik J, Tapajna M, Rosova A, Aidla A, Dobrocka E, Huskova K (2009) Epitaxial growth of high-kappa TiO2 rutile films on RuO2 electrodes. J Vac Sci Technol B 27(1):266–270

    Article  Google Scholar 

  6. Swerts J et al (2014) Leakage control in 0.4 nm EOT Ru/SrTiOx /Ru metal-insulator-metal capacitors: process implications. IEEE Electron Device Lett. 35(7):753–755

    Article  CAS  Google Scholar 

  7. Lee JM et al (2017) Novel approach for the reduction of leakage current characteristics of 20 nm DRAM capacitors with Zro2–based high-k dielectrics. IEEE Electron Device Lett 38(11):1524–1527

    Article  CAS  Google Scholar 

  8. Sharroush SM (2019) A predischarged bitline 1T–1C DRAM readout scheme. Microelectron J 83:168–184

    Article  Google Scholar 

  9. Kurinec SK, Iniewaki K (2017) Nanoscale semiconductor memories: technology and applications. CRC Press, Boca Raton

    Book  Google Scholar 

  10. Kim Y, Kwon M-W, Ryoo K-C, Cho S, Park B-G (2018) Design and electrical characterization of 2-T thyristor RAM with low power consumption. IEEE Electron Device Lett 39(3):355–358

    Article  CAS  Google Scholar 

  11. Song SH, Kim MW, Yoo SD, Shim TH, Park JG (2018) Design of two-terminal-electrode vertical thyristor as cross-point memory cell without selector. Appl. Phys. Lett. 113(5):052103-1-052103–5

    Article  Google Scholar 

  12. Kim H, Cho H, Kong BD, Kim J-W, Meyyappan M, Baek C-K (2020) Electrical and data-retention characteristics of two-terminal thyristor random access memory. IEEE Open J Nanotechno 1:163–169

    Article  Google Scholar 

  13. Paolucci GM et al (2013) Dynamic analysis of current-voltage characteristics of nanoscale gated-thyristors. IEEE Electron Device Lett 34(5):629–631

    Article  Google Scholar 

  14. Mulaosmanovic H et al (2014) Working principles of a DRAM cell based on gated-thyristor bistability. IEEE Electron Device Lett 35(9):921–923

    Article  Google Scholar 

  15. Mulaosmanovic H et al (2015) Investigation of the turn-ON of T-RAM cells under transient conditions. IEEE Trans Electron Devices 62(4):1170–1176

    Article  CAS  Google Scholar 

  16. Mulaosmanovic H et al (2014) Data regeneration and disturb immunity of T-RAM cells. In: Proceedings of the 44th ESSDERC, pp 46–49

  17. Jeong H, Song K-W, Park IH, Kim T-H, Lee YS, Kim S-G, Seo J, Cho K, Lee K, Shin H, Lee JD, Park B-G (2007) A new capacitorless 1T DRAM cell: surrounding gate MOSFET with vertical channel (SGVC cell). IEEE Trans Nanotechnol 6(3):352–357

    Article  Google Scholar 

  18. Moon D-I, Kim J-Y, Moon J-B, Kim D-O, Choi Y-K (2014) Evolution of unified-RAM: 1T-DRAM and BE-SONOS built on a highly scaled vertical channel. IEEE Trans Electron Devices 61(1):60–65

    Article  CAS  Google Scholar 

  19. Sentaurus TCAD Version O-2018.06 (2018) Synopsys, Mountain View, CA, USA

  20. Lim D, Son J, Cho K, Kim S (2020) Quasi-nonvolatile silicon memory device. Adv Mater Technol 5(12), Art. no. 2000915

  21. Klassen DBM (1992) A unified mobility model for device simulation-I: Model equations and concentration dependence. Solid-State Electron 35(7):953–959

    Article  Google Scholar 

  22. Slotboom J, De Graaff H (1976) Measurements of bandgap narrowing in si bipolar transistors. Solid-State Electron 19(10):857–862

    Article  CAS  Google Scholar 

  23. Schenk A (1992) A model for the field and temperature dependence of Shockley-Read-Hall lifetimes in silicon. Solid-State Electron 35(11):1585–1596

    Article  CAS  Google Scholar 

  24. Richter A, Werner F, Cuevas A, Schmidt J, Glunz SW (2012) Improved parameterization of auger recombination in silicon. Phys Rev B Condens Matter 86:165202

    Article  Google Scholar 

  25. Van Overstraeten R, De Man H (1970) Measurement of the ionization rates in diffused silicon p-n junctions. Solid-State Electron 13:583–608

    Article  Google Scholar 

  26. Hurkx GAM, Klaassen DBM, Knuvers MPG (1992) A new recombination model for device simulation including tunneling. IEEE Trans Electron Dev 39(2):331–338

    Article  Google Scholar 

  27. JESD79-4A (2013) JEDEC Committee JC-42.3 Std. DDR4 SDRAM STANDARD

Download references


This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea Government (MSIT) (NRF- 2020R1A2C2006515), by POSTECH-Samsung Electronics Industry-Academia Cooperative Research Center and by IC Design Education Center (IDEC), Korea.

Author information

Authors and Affiliations



HWK conceived the idea, designed and performed the simulation, analyzed the data and wrote the manuscript. HSC guided and supervised the whole project. HTK, MHS and SHL supported simulation and characterization of the devices. BDK and CKB provided advice on the simulation work and contributed to manuscript preparation. All authors critically read and approved the final manuscript.

Corresponding author

Correspondence to Hyeonsu Cho.

Ethics declarations

Competing interests

The authors declare that they have no competing interests.

Additional information

Publisher's Note

Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Rights and permissions

Open Access This article is licensed under a Creative Commons Attribution 4.0 International License, which permits use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons licence, and indicate if changes were made. The images or other third party material in this article are included in the article's Creative Commons licence, unless indicated otherwise in a credit line to the material. If material is not included in the article's Creative Commons licence and your intended use is not permitted by statutory regulation or exceeds the permitted use, you will need to obtain permission directly from the copyright holder. To view a copy of this licence, visit

Reprints and Permissions

About this article

Verify currency and authenticity via CrossMark

Cite this article

Kim, H., Cho, H., Kwak, HT. et al. Highly Reliable Memory Operation of High-Density Three-Terminal Thyristor Random Access Memory. Nanoscale Res Lett 17, 28 (2022).

Download citation

  • Received:

  • Accepted:

  • Published:

  • DOI:


  • Capacitorless 1T DRAM
  • Memory array operation
  • Memory disturbance
  • Three-terminal TRAM
  • Gated-thyristors