Fig. 12From: Design of GAA Nanosheet Ferroelectric Area Tunneling FET and Its Significance with DC/RF Characteristics Including Linearity AnalysesComparison of SE variation with supply voltage scaling. It clears that the proposed structure (FATFET) reduces SE by 2-order (both in logic and memory environments) due to its high \(I_{{\rm on}}{/}I_{{\rm off}}\) ratioBack to article page